View M38259EFDFP_985577.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

description the 3825 group is the 8-bit microcomputer based on the 740 fam- ily core technology. the 3825 group has the lcd drive control circuit, an 8-channel a- d converter, and a serial i/o as additional functions. the various microcomputers in the 3825 group include variations of internal memory size and packaging. for details, refer to the section on part numbering. for details on availability of microcomputers in the 3825 group, refer the section on group expansion. features basic machine-language instructions ....................................... 71 the minimum instruction execution time ............................ 0.5 ? (at 8 mhz oscillation frequency) memory size rom .................................................................. 4 k to 60 k bytes ram ................................................................. 192 to 2048 bytes programmable input/output ports ............................................. 43 software pull-up/pull-down resistors (ports p0?8) interrupts .................................................. 17 sources, 16 vectors (includes key input interrupt) timers ........................................................... 8-bit ? 3, 16-bit ? 2 serial i/o ...................... 8-bit ? 1 (uart or clock-synchronized) a-d converter .................................................. 8-bit ? 8 channels lcd drive control circuit bias ................................................................................... 1/2, 1/3 duty ............................................................................ 1/2, 1/3, 1/4 common output .......................................................................... 4 segment output ......................................................................... 40 2 clock generating circuits (connect to external ceramic resonator or quartz-crystal oscillator) power source voltage in high-speed mode ................................................... 4.0 to 5.5 v in middle-speed mode ............................................... 2.5 to 5.5 v (m version: 2.2 to 5.5 v) (extended operating temperature version: 3.0 to 5.5 v) in low-speed mode ..................................................... 2.5 to 5.5 v (m version: 2.2 to 5.5 v) (extended operating temperature version: 3.0 to 5.5 v) power dissipation in high-speed mode ........................................................... 32 mw (at 8 mhz oscillation frequency, at 5 v power source voltage) in low-speed mode .............................................................. 45 w (at 32 khz oscillation frequency, at 3 v power source voltage) operating temperature range ................................... 20 to 85? (extended operating temperature version: ?0 to 85?) applications camera, household appliances, consumer electronics, etc. 3825 group mitsubishi microcomputers single-chip 8-bit cmos microcomputer package type : 100p6s-a (100-pin plastic-molded qfp) fig. 1 pin configuration of m38258mcmxxxfp (the pin configuration of 100d0 is same as this.) pin configuration (top view) 1 2 3 4 5 6 7 8 9 101112131 41 51 61 71 81 92 02122232425262 72 82 93 0 3 1 3 2 33 34 35 3 6 3 7 3 8 3 9 40 41 4 2 43 4 4 4 5 4 6 4 7 4 8 49 50 5 1 5 2 5 3 5 4 5 5 5 6 5 7 5 8 5 9 6 0 6 1 62 63 64 65 66 67 68 69 70 7 1 72 73 7 4 7 5 7 6 7 7 7 8 7 9 8 0 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 10 0 m38258mcmxxxfp s e g 9 p 3 1 / s e g 1 9 p 3 0 / s e g 1 8 p 3 2 / s e g 2 0 p 3 3 / s e g 2 1 p 3 4 / s e g 2 2 s e g 1 0 s e g 1 1 s e g 1 2 s e g 1 3 s e g 1 4 s e g 1 5 p 3 5 / s e g 2 3 p 3 6 / s e g 2 4 p 3 7 / s e g 2 5 p 0 0 / s e g 2 6 p 0 1 / s e g 2 7 p 0 2 / s e g 2 8 p 0 3 / s e g 2 9 p 0 4 / s e g 3 0 p 0 5 / s e g 3 1 p 0 6 / s e g 3 2 p 0 7 / s e g 3 3 p 1 0 / s e g 3 4 p 1 1 / s e g 3 5 p 1 2 / s e g 3 6 p 1 3 / s e g 3 7 p 1 4 / s e g 3 8 p 1 5 / s e g 3 9 c 1 v l 1 p 6 7 / a n 7 p 6 6 / a n 6 p 6 5 / a n 5 p 6 4 / a n 4 p 6 3 / a n 3 p 6 2 / a n 2 p 6 1 / a n 1 p 6 0 / a n 0 p 5 7 / a d t p 5 6 / t o u t p 5 5 / c n t r 1 p 5 4 / c n t r 0 p 5 3 / r t p 1 p 5 2 / r t p 0 p 5 1 / i n t 3 p 5 0 / i n t 2 p 4 6 / s c l k p 4 5 / t x d p 4 4 / r x d p 4 3 / i n t 1 p 4 2 / i n t 0 p 4 1 / f ( x i n ) / 5 / f ( x i n ) / 1 0 p 4 0 / f ( x i n ) / f ( x i n ) / 2 p 7 7 p 7 6 p 7 5 p 7 4 c 2 v l2 v l3 c o m 0 c o m 1 c o m 2 v r e f a v s s v cc seg 8 seg 0 s e g 1 s e g 2 s e g 4 s e g 5 s e g 6 s e g 7 s e g 3 p7 2 p7 3 p7 1 p 7 0 p 8 1 / x c i n p 8 0 / x c o u t x i n x o u t v s s p2 7 p2 6 p 2 5 p2 4 p 2 3 p 2 1 p 1 6 p 2 2 p2 0 p1 7 r e s e t s e g 1 6 s e g 1 7 c o m 3 p 4 7 / s r d y
single-chip 8-bit cmos microcomputer mitsubishi microcomputers 3825 group 2 package type : gp ........................... 100p6q-a (100-pin plastic-molded lqfp) package type : hp ........................... 100pfb-a (100-pin plastic-molded tqfp) pin configuration (top view) fig. 2 pin configuration of m38258mcmxxxgp, m38258mcmxxxhp 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 2 6 27 28 2 9 3 0 3 1 32 3 3 3 4 35 36 3 7 3 8 39 4 0 4 1 4 2 4 3 4 4 4 5 4 6 4 7 4 8 4 9 5 0 5 1 5 2 5 3 5 4 5 5 5 6 5 7 58 5 9 6 0 6 1 62 6 3 64 65 66 67 68 6 9 70 7 1 7 2 73 74 75 7 6 7 7 7 8 7 9 8 0 8 1 8 2 8 3 8 4 8 5 8 6 8 7 88 8 9 9 0 9 1 92 9 3 9 4 9 5 9 6 97 98 9 9 0 0 1 m 3 8 2 5 8 m c m x x x g p m 3 8 2 5 8 m c m x x x h p s e g 1 2 s e g 1 1 s e g 1 0 s e g 9 s e g 8 s e g 7 s e g 6 s e g 5 s e g 4 s e g 3 s e g 2 seg 1 s e g 0 v c c v r e f av ss c o m 3 c o m 2 c o m 1 com 0 v l 3 v l 2 c 2 c 1 v l 1 p 6 7 / a n 7 p 6 6 / a n 6 p 6 5 / a n 5 p 6 4 / a n 4 p 6 3 / a n 3 p 6 2 / a n 2 p 6 1 / a n 1 p 6 0 / a n 0 p 5 7 / a d t p 5 6 / t o u t p 5 5 / c n t r 1 p 5 4 / c n t r 0 p 5 3 / r t p 1 p 5 2 / r t p 0 p 5 1 / i n t 3 p 5 0 / i n t 2 p 4 6 / s c l k p 4 5 / t x d p 4 4 / r x d p 4 3 / i n t 1 p 4 2 / i n t 0 p 4 1 / f ( x i n ) / 5 / f ( x i n ) / 1 0 p 4 0 / f ( x i n ) / f ( x i n ) / 2 p 7 7 p 4 7 / s r d y p 7 2 p7 3 p 7 1 p7 0 p 8 1 / x c i n p8 0 /x cout x i n x o u t v ss p 2 7 p 2 6 p2 5 p 2 4 p 2 3 p 2 1 p 1 6 p 2 2 p 2 0 p 1 7 r e s e t p 7 6 p7 5 p 7 4 p 1 5 / s e g 3 9 p 1 4 / s e g 3 8 p 3 1 / s e g 1 9 p 3 0 / s e g 1 8 p 3 2 / s e g 2 0 p 3 3 / s e g 2 1 p 3 4 / s e g 2 2 s e g 1 3 s e g 1 4 s e g 1 5 p 3 5 / s e g 2 3 p 3 6 / s e g 2 4 p 3 7 / s e g 2 5 p 0 0 / s e g 2 6 p 0 1 / s e g 2 7 p 0 2 / s e g 2 8 p 0 3 / s e g 2 9 p 0 4 / s e g 3 0 p 0 5 / s e g 3 1 p 0 6 / s e g 3 2 p 0 7 / s e g 3 3 p 1 0 / s e g 3 4 p 1 1 / s e g 3 5 p 1 2 / s e g 3 6 p 1 3 / s e g 3 7 s e g 1 6 s e g 1 7
single-chip 8-bit cmos microcomputer mitsubishi microcomputers 3825 group 3 functional block diagram (package : 100p6s-a) fig. 3 functional block diagram a d t c n t r 0 , c n t r 1 t o u t c p u a x y s p c h p c l p s r o m s i / o ( 8 ) v l 1 v l 2 v l 3 c o m 0 c o m 1 c o m 2 c o m 3 3 8 l c d d r i v e c o n t r o l c i r c u i t r a m l c d d i s p l a y r a m ( 2 0 b y t e s ) t i m e r x ( 1 6 ) t i m e r y ( 1 6 ) t i m e r 1 ( 8 )t i m e r 2 ( 8 ) t i m e r 3 ( 8 ) d a t a b u s c l o c k g e n e r a t i n g c i r c u i t c l o c k i n p u t x i n c l o c k o u t p u t x o u t x c o u t s u b - c l o c k o u t p u t x c i n s u b - c l o c k i n p u t v c c r e s e t i n p u t ( 5 v ) r e s e t k e y - o n w a k e u p r e a l t i m e p o r t f u n c t i o n i n t 0 , i n t 1 a - d c o n v e r t e r ( 8 ) r t p 0 , r t p 1 3 9 3 5 9 1 4 0 v s s ( 0 v ) 9 9 9 8 9 7 9 6 9 5 9 4 9 0 8 9 8 8 8 7 8 6 8 5 8 4 8 3 8 2 8 1 8 0 7 9 s e g 1 1 s e g 1 s e g 2 s e g 3 s e g 4 s e g 5 s e g 6 s e g 7 s e g 8 s e g 9 s e g 1 0 s e g 0 5 76 4 o u t p u t p o r t p 0 p 0 ( 8 ) 6 3 6 2 6 1 6 0 5 9 5 8 4 95 6 o u t p u t p o r t p 1 p 1 ( 8 ) 5 5 5 4 5 3 5 2 5 1 5 0 4 14 8 i / o p o r t p 2 p 2 ( 8 ) 4 7 4 6 4 5 4 4 4 3 4 2 p 4 ( 8 ) 1 92 6 i / o p o r t p 4 2 5 2 4 2 3 2 2 2 1 2 0 1 11 8 i / o p o r t p 5 p 5 ( 8 ) 1 7 1 6 1 5 1 4 1 3 1 2 i n t 2 , i n t 3 9 3 9 2 v r e f a v s s ( 0 v ) p 6 ( 8 ) 3 1 0 i / o p o r t p 6 9 8 7 6 5 4 p 8 ( 2 ) x c i n x c o u t 3 7 3 6 i / o p o r t p 8 1 2 1 0 0 c 1 c 2 7 8 7 7 7 6 7 5 7 4 7 3 s e g 1 7 s e g 1 2 s e g 1 3 s e g 1 4 s e g 1 5 s e g 1 6 o u t p u t p o r t p 3 p 3 ( 8 ) 6 57 2 7 1 7 0 6 9 6 8 6 7 6 6 p 7 ( 8 ) 2 73 4 i / o p o r t p 7 3 3 3 2 3 1 3 0 2 9 2 8
single-chip 8-bit cmos microcomputer mitsubishi microcomputers 3825 group 4 pin description table 1. pin description (1) function apply voltage of power source to v cc , and 0 v to v ss . (for the limits of v cc, refer to recom- mended operating conditions .) reference voltage input pin for a-d converter. gnd input pin for a-d converter. connect to v ss . reset input pin for active l input and output pins for the main clock generating circuit. feedback resistor is built in between x in pin and x out pin. connect a ceramic resonator or a quartz-crystal oscillator between the x in and x out pins to set the oscillation frequency. if an external clock is used, connect the clock source to the x in pin and leave the x out pin open. this clock is used as the oscillating source of system clock. input 0 v l1 v l2 v l3 v cc voltage input 0 v l3 voltage to lcd external capacitor pins for a voltage multiplier (3 times) of lcd contorl. lcd common output pins com 2 and com 3 are not used at 1/2 duty ratio. com 3 is not used at 1/3 duty ratio. lcd segment output pins 8-bit output port cmos 3-state output structure pull-down control is enabled. port output control is enabled. 6-bit output port cmos 3-state output structure pull-down control is enabled. port output control is enabled. 2-bit i/o port cmos compatible input level cmos 3-state output structure i/o direction register allows each pin to be individually programmed as either input or output. pull-up control is enabled. 8-bit input port cmos compatible input level cmos 3-state output structure i/o direction register allows each pin to be individually programmed as either input or output. pull-up control is enabled. 8-bit output port cmos 3-state output structure pull-down control is enabled. port output control is enabled. lcd segment pins key input (key-on wake up) interrupt input pins lcd segment pins pin v cc , v ss v ref av ss reset x in x out v l1 v l3 c 1 , c 2 com 0 com 3 seg 0 seg 17 p0 0 / seg 26 p0 7 / seg 33 p1 0 / seg 34 p1 5 / seg 39 p1 6 , p1 7 p2 0 p2 7 p3 0 / seg 18 p3 7 / seg 25 name power source analog reference voltage analog power source reset input clock input clock output lcd power source charge-pump capacitor pin common output segment output output port p0 output port p1 i/o port p1 i/o port p2 output port p3 function except a port function
single-chip 8-bit cmos microcomputer mitsubishi microcomputers 3825 group 5 function 8-bit i/o port cmos compatible input level cmos 3-state output structure i/o direction register allows each pin to be individually programmed as either input or output. pull-up control is enabled. 8-bit i/o port cmos compatible input level cmos 3-state output structure i/o direction register allows each pin to be individually programmed as either input or output. pull-up control is enabled. 8-bit i/o port cmos compatible input level cmos 3-state output structure i/o direction register allows each pin to be individually programmed as either input or output. pull-up control is enabled. 1-bit input port cmos compatible input level 7-bit i/o port cmos compatible input level cmos 3-state output structure i/o direction register allows each pin to be individually programmed as either input or output. pull-up control is enabled. 2-bit i/o port cmos compatible input level cmos 3-state output structure i/o direction register allows each pin to be individually programmed as either input or output. pull-up control is enabled. pin p4 0 /f(x in )/ f(x in )/2, p4 1 /f(x in )/5/ f(x in )/10 p4 2 /int 0 , p4 3 /int 1 p4 4 /r x d, p4 5 /t x d, p4 6 /s clk , p4 7 /s rdy p5 0 /int 2 , p5 1 /int 3 p5 2 /rtp 0 , p5 3 /rtp 1 p5 4 /cntr 0 , p5 5 /cntr 1 p5 6 /t out p5 7 /adt p6 0 /an 0 p6 7 /an 7 p7 0 p7 1 p7 7 p8 0 /x cout , p8 1 /x cin name i/o port p4 i/o port p5 i/o port p6 input port p7 i/o port p7 i/o port p8 function except a port function clock output pins interrupt input pins serial i/o function pins interrupt input pins real time port function pins timers x, y functions pins timer 2 output pin a-d trigger input pin a-d conversion input pins table 2. pin description (2) sub-clock generating circuit i/o pins (connect a resonator. external clock cannot be used.)
single-chip 8-bit cmos microcomputer mitsubishi microcomputers 3825 group 6 part numbering fig. 4 part numbering m 3 8 2 5 8 m c m x x x h p product rom/prom size 1 2 3 4 5 6 7 8 : 4096 bytes : 8192 bytes : 12288 bytes : 16384 bytes : 20480 bytes : 24576 bytes : 28672 bytes : 32768 bytes t h e f i r s t 1 2 8 b y t e s a n d t h e l a s t 2 b y t e s o f r o m a r e r e s e r v e d a r e a s ; t h e y c a n n o t b e u s e d . m e m o r y t y p e m e : mask rom version : eprom or one time prom version r a m s i z e 0 1 2 3 4 5 6 7 8 9 : 192 bytes : 256 bytes : 384 bytes : 512 bytes : 640 bytes : 768 bytes : 896 bytes : 1024 bytes : 1536 bytes : 2048 bytes r o m n u m b e r o m i t t e d i n o n e t i m e p r o m v e r s i o n s h i p p e d i n b l a n k a n d e p r o m v e r s i o n . n o r m a l l y , u s i n g h y p h e n w h e n e l e c t r i c a l c h a r a c t e r i s t i c , o r d i v i s i o n o f q u a l i t y i d e n t i f i c a t i o n c o d e u s i n g a l p h a n u m e r i c c h a r a c t e r : s t a n d a r d d : e x t e n d e d o p e r a t i n g t e m p e r a t u r e v e r s i o n m : m v e r s i o n p a c k a g e t y p e f p h p g p f s : 100p6s-a package : 100pfb-a package : 100p6q-a package : 100d0 package 9 a b c d e f : 36864 bytes : 40960 bytes : 45056 bytes : 49152 bytes : 53248 bytes : 57344 bytes : 61440 bytes
single-chip 8-bit cmos microcomputer mitsubishi microcomputers 3825 group 7 group expansion (standard, one time prom version, eprom version) mitsubishi plans to expand the 3825 group(standard, one time prom version, eprom version) as follows. memory type support for mask rom, one time prom, and eprom versions. memory size rom size ............................................................ 16 k to 60 kbytes ram size ............................................................ 640 to 2048 bytes packages 100pfb-a ................................ 0.4 mm-pitch plastic molded tqfp 100p6q-a ................................ 0.5 mm-pitch plastic molded lqfp 100p6s-a ................................ 0.65 mm-pitch plastic molded qfp 100d0 ................... 0.65 mm-pitch ceramic lcc (eprom version) memory expansion plan fig. 5 memory expansion plan 6 0 k 5 6 k 5 2 k 4 8 k 4 4 k 3 6 k 32k 2 8 k 24k 2 0 k 16k 1 2 k 8k 4 k 40k r o m s i z e ( b y t e s ) 256 1 , 0 2 41 , 5 3 6 2,048 r a m s i z e ( b y t e s ) m a s s p r o d u c t mass product m a s s p r o d u c t m38254m6 m a s s p r o d u c t 5 1 27 6 8 6 4 0 m 3 8 2 5 4 m 4 m 3 8 2 5 7 m 8 / e 8 m38259ef
single-chip 8-bit cmos microcomputer mitsubishi microcomputers 3825 group 8 currently products are listed below. table 3. list of products as of dec. 2000 remarks mask rom version mask rom version mask rom version mask rom version mask rom version one time prom version (blank) mask rom version one time prom version (blank) eprom version one time prom version (blank) one time prom version (blank) one time prom version (blank) eprom version package 100p6s-a 100p6q-a 100p6s-a 100p6q-a 100p6s-a 100p6s-a 100p6q-a 100p6q-a 100d0 100p6s-a 100pfb-a 100p6q-a 100d0 product m38254m4-xxxfp m38254m4-xxxgp m38254m6-xxxfp m38254m6-xxxgp m38257m8-xxxfp m38257e8fp m38257m8-xxxgp m38257e8gp m38257e8fs m38259effp m38259efhp m38259efgp m38259effs ram size (bytes) 640 640 16384 (16254) rom size (bytes) rom size for user in ( ) 32768 (32638) 24576 (24446) 61440 (61310) 2048 1024
single-chip 8-bit cmos microcomputer mitsubishi microcomputers 3825 group 9 group expansion (extended operating temperature version) mitsubishi plans to expand the 3825 group (extended operating temperature version) as follows. memory type support for mask rom, one time prom version. memory size rom size ............................................................ 16 k to 60 kbytes ram size ............................................................ 640 to 2048 bytes packages 100p6s-a ................................ 0.65 mm-pitch plastic molded qfp memory expansion plan currently products are listed below. table 4. list of products for extended operating temperature version as of dec. 2000 fig. 6 memory expansion plan for extended operating temperature version remarks mask rom version mask rom version mask rom version mask rom version one time prom version (blank) ram size (bytes) 640 640 1024 1536 2048 16384 (16254) 24576 (24446) 32768 (32638) 49152 (49022) 61440 (61310) package 100p6s-a 100p6s-a 100p6s-a 100p6s-a 100p6s-a product m38254m4dxxxfp m38254m6dxxxfp m38257m8dxxxfp m38258mcdxxxfp M38259EFDFP rom size (bytes) rom size for user in ( ) m a s s p r o d u c t 6 0 k 5 6 k 5 2 k 4 8 k 4 4 k 36k 3 2 k 2 8 k 24k 20k 16k 1 2 k 8 k 4k 4 0 k r o m s i z e ( b y t e s ) 2 5 61 , 5 3 6 2,048 ram size (bytes) mass product mass product mass product mass product m38254m6d 5 1 2768 6 4 0 m 3 8 2 5 4 m 4 d 1 , 0 2 4 m38257m8d m38258mcd m 3 8 2 5 9 e f d
single-chip 8-bit cmos microcomputer mitsubishi microcomputers 3825 group 10 group expansion (m version) mitsubishi plans to expand the 3825 group (m version) as follows. memory type support for mask rom version. memory size rom size ......................................................................... 48 kbytes ram size ....................................................................... 1536 bytes packages 100pfb-a ................................ 0.4 mm-pitch plastic molded tqfp 100p6q-a ................................ 0.5 mm-pitch plastic molded lqfp 100p6s-a ................................ 0.65 mm-pitch plastic molded qfp memory expansion plan currently products are listed below. table 5. list of products for low power source version as of dec. 2000 fig. 7 memory expansion plan for m version ram size (bytes) 49152 (49022) package 100p6s-a 100pfb-a 100p6q-a product m38258mcmxxxfp m38258mcmxxxhp m38258mcmxxxgp rom size (bytes) rom size for user in ( ) 1536 remarks mask rom version mask rom version mask rom version 6 0 k 5 6 k 5 2 k 48k 44k 3 6 k 3 2 k 28k 2 4 k 2 0 k 1 6 k 12k 8k 4 k 4 0 k r o m s i z e ( b y t e s ) 2 5 65 1 27 6 8 1,024 1 , 5 3 62 , 0 4 8 r a m s i z e ( b y t e s ) mass product m 3 8 2 5 8 m c m
single-chip 8-bit cmos microcomputer mitsubishi microcomputers 3825 group 11 functional description central processing unit (cpu) the 3825 group uses the standard 740 family instruction set. re- fer to the table of 740 family addressing modes and machine instructions or the 740 family software manual for details on the instruction set. machine-resident 740 family instructions are as follows: the fst and slw instruction cannot be used. the stp, wit, mul, and div instruction can be used. [accumulator (a)] the accumulator is an 8-bit register. data operations such as data transfer, etc., are executed mainly through the accumulator. [index register x (x)] the index register x is an 8-bit register. in the index addressing modes, the value of the operand is added to the contents of register x and specifies the real address. [index register y (y)] the index register y is an 8-bit register. in partial instruction, the value of the operand is added to the contents of register y and specifies the real address. [stack pointer (s)] the stack pointer is an 8-bit register used during subroutine calls and interrupts. this register indicates start address of stored area (stack) for storing registers during subroutine calls and interrupts. the low-order 8 bits of the stack address are determined by the contents of the stack pointer. the high-order 8 bits of the stack address are determined by the stack page selection bit. if the stack page selection bit is 0 , the high-order 8 bits becomes 00 16 . if the stack page selection bit is 1 , the high-order 8 bits becomes 01 16 . the operations of pushing register contents onto the stack and popping them from the stack are shown in figure 9. store registers other than those described in figure 9 with pro- gram when the user needs them during interrupts or subroutine calls. [program counter (pc)] the program counter is a 16-bit counter consisting of two 8-bit registers pc h and pc l . it is used to indicate the address of the next instruction to be executed. fig. 8 740 family cpu register structure a accumulator b7 b7 b7 b7 b0 b7 b15 b0 b7 b0 b0 b0 b0 x index register x y index register y s stack pointer pc l program counter pc h n v t b d i z c processor status register (ps) carry flag zero flag interrupt disable flag decimal mode flag break flag index x mode flag overflow flag negative flag
single-chip 8-bit cmos microcomputer mitsubishi microcomputers 3825 group 12 table 6 push and pop instructions of accumulator or processor status register accumulator processor status register push instruction to stack pha php pop instruction from stack pla plp fig. 9 register push and pop at interrupt generation and subroutine call n o t e : c o n d i t i o n f o r a c c e p t a n c e o f a n i n t e r r u p t i n t e r r u p t e n a b l e f l a g i s 1 e x e c u t e j s r o n - g o i n g r o u t i n e m ( s )( p c h ) ( s ) ( s ) 1 m ( s )( p c l ) e x e c u t e r t s ( p c l )m ( s ) ( s ) ( s ) 1 ( s ) ( s ) + 1 ( s ) ( s ) + 1 ( p c h )m ( s ) s u b r o u t i n e p o p re t u r n a d d r e s s f r o m s t a c k p u s h r e t u r n a d d r e s s o n s t a c k m ( s )( p s ) e x e c u t e r t i ( p s )m ( s ) ( s ) ( s ) 1 ( s ) ( s ) + 1 i n t e r r u p t s e r v i c e r o u t i n e p o p c o n t e n t s o f p r o c e s s o r s t a t u s r e g i s t e r f r o m s t a c k m ( s )( p c h ) ( s ) ( s ) 1 m ( s )( p c l ) ( s ) ( s ) 1 ( p c l )m ( s ) ( s ) ( s ) + 1 ( s ) ( s ) + 1 ( p c h )m ( s ) p o p r e t u r n a d d r e s s f r o m s t a c k i f l a g i s s e t f r o m 0 t o 1 f e t c h t h e j u m p v e c t o r p u s h r e t u r n a d d r e s s o n s t a c k p u s h c o n t e n t s o f p r o c e s s o r s t a t u s r e g i s t e r o n s t a c k i n t e r r u p t r e q u e s t ( n o t e ) i n t e r r u p t d i s a b l e f l a g i s 0
single-chip 8-bit cmos microcomputer mitsubishi microcomputers 3825 group 13 [processor status register (ps)] the processor status register is an 8-bit register consisting of 5 flags which indicate the status of the processor after an arithmetic operation and 3 flags which decide mcu operation. branch opera- tions can be performed by testing the carry (c) flag , zero (z) flag, overflow (v) flag, or the negative (n) flag. in decimal mode, the z, v, n flags are not valid. bit 0: carry flag (c) the c flag contains a carry or borrow generated by the arithmetic logic unit (alu) immediately after an arithmetic operation. it can also be changed by a shift or rotate instruction. bit 1: zero flag (z) the z flag is set if the result of an immediate arithmetic operation or a data transfer is 0 , and cleared if the result is anything other than 0 . bit 2: interrupt disable flag (i) the i flag disables all interrupts except for the interrupt generated by the brk instruction. interrupts are disabled when the i flag is 1 . bit 3: decimal mode flag (d) the d flag determines whether additions and subtractions are executed in binary or decimal. binary arithmetic is executed when this flag is 0 ; decimal arithmetic is executed when it is 1 . decimal correction is automatic in decimal mode. only the adc bit 4: break flag (b) the b flag is used to indicate that the current interrupt was generated by the brk instruction. the brk flag in the processor status register is always 0 . when the brk instruction is used to generate an interrupt, the processor status register is pushed onto the stack with the break flag set to 1 . bit 5: index x mode flag (t) when the t flag is 0 , arithmetic operations are performed between accumulator and memory. when the t flag is 1 , direct arithmetic operations and direct data transfers are enabled between memory locations. bit 6: overflow flag (v) the v flag is used during the addition or subtraction of one byte of signed data. it is set if the result exceeds +127 to -128. when the bit instruction is executed, bit 6 of the memory location operated on by the bit instruction is stored in the overflow flag. bit 7: negative flag (n) the n flag is set if the result of an arithmetic operation or data transfer is negative. when the bit instruction is executed, bit 7 of the memory location operated on by the bit instruction is stored in the negative flag. table 7 set and clear instructions of each bit of processor status register set instruction clear instruction c flag sec clc z flag i flag sei cli d flag sed cld b flag t flag set clt v flag clv n flag
single-chip 8-bit cmos microcomputer mitsubishi microcomputers 3825 group 14 [cpu mode register (cpum)] 003b 16 the cpu mode register contains the stack page selection bit and the internal system clock selection bit. the cpu mode register is allocated at address 003b 16 . fig. 10 structure of cpu mode register n o t a v a i l a b l e p rocessor mo d e bi ts b1 b0 0 0 : single-chip mode 0 1 : 1 0 : 1 1 : stack page selection bit 0 : 0 page 1 : 1 page not used (returns 1 when read) (do not write 0 to this bit) port x c switch bit 0 : i/o port function (stop oscillating) 1 : x cin x cout oscillating function main clock (x in x out ) stop bit 0 : oscillating 1 : stopped main clock division ratio selection bit 0 : f(x in )/2 (high-speed mode) 1 : f(x in )/8 (middle-speed mode) internal system clock selection bit 0 : x in x out selected (middle-/high-speed mode) 1 : x cin x cout selected (low-speed mode) cpu mo d e reg i ster ( c p u m ( c m ) : a d d r e s s 0 0 3 b 1 6 ) b 7 b 0
single-chip 8-bit cmos microcomputer mitsubishi microcomputers 3825 group 15 memory special function register (sfr) area the special function register area in the zero page contains con- trol registers such as i/o ports and timers. ram ram is used for data storage and for stack area of subroutine calls and interrupts. rom the first 128 bytes and the last 2 bytes of rom are reserved for device testing and the rest is user area for storing programs. interrupt vector area the interrupt vector area contains reset and interrupt vectors. zero page the 256 bytes from addresses 0000 16 to 00ff 16 are called the zero page area. the internal ram and the special function regis- ters (sfr) are allocated to this area. the zero page addressing mode can be used to specify memory and register addresses in the zero page area. access to this area with only 2 bytes is possible in the zero page addressing mode. special page the 256 bytes from addresses ff00 16 to ffff 16 are called the special page area. the special page addressing mode can be used to specify memory addresses in the special page area. ac- cess to this area with only 2 bytes is possible in the special page addressing mode. fig. 11 memory map diagram 192 256 384 512 640 768 896 1024 1536 2048 00 ff 16 013f 16 01bf 16 023f 16 02bf 16 033f 16 03bf 16 043f 16 063f 16 083f 16 ram area r a m s i z e ( b y t e s ) a d d r e s s x x x x 1 6 409 6 819 2 1228 8 1638 4 2048 0 2457 6 2867 2 3276 8 3686 4 4096 0 4505 6 4915 2 5324 8 5734 4 6144 0 f 000 16 e000 16 d000 16 c000 16 b000 16 a000 16 9000 16 8000 16 7000 16 6000 16 5000 16 4000 16 3000 16 2000 16 1000 16 f 080 16 e080 16 d080 16 c080 16 b080 16 a080 16 9080 16 8080 16 7080 16 6080 16 5080 16 4080 16 3080 16 2080 16 1080 16 rom area rom s i ze (bytes) a d d r e s s y y y y 1 6 a d d r e s s z z z z 1 6 0100 16 0000 16 0040 16 0840 16 ff 00 16 ffdc 16 f f f e 1 6 ffff 16 xxxx 16 yyyy 16 zzzz 16 ram r o m 0054 16 r eserve d area s f r a r e a n ot use d i n t e r r u p t v e c t o r a r e a r eserve d rom area (128 bytes) z e r o p a g e s pec i a l page lcd di sp l ay ram area r e s e r v e d r o m a r e a
single-chip 8-bit cmos microcomputer mitsubishi microcomputers 3825 group 16 fig. 12 memory map of special function register (sfr) 0020 16 0021 16 0022 16 0023 16 0024 16 0025 16 0026 16 0027 16 0028 16 0029 16 002 a 16 002 b 16 0 0 2 c 1 6 0 0 2 d 1 6 002 e 16 002 f 16 0030 16 0031 16 0032 16 0033 16 0034 16 0035 16 0036 16 0037 16 0038 16 0039 16 003 a 16 003 b 16 0 0 3 c 1 6 003 d 16 003 e 16 003 f 16 0 0 0 0 1 6 0001 16 0002 16 0 0 0 3 1 6 0 0 0 4 1 6 0005 16 0 0 0 6 1 6 0 0 0 7 1 6 0 0 0 8 1 6 0 0 0 9 1 6 000 a 16 0 0 0 b 1 6 000 c 16 000 d 16 0 0 0 e 1 6 000 f 16 0010 16 0011 16 0012 16 0 0 1 3 1 6 0 0 1 4 1 6 0015 16 0016 16 0017 16 0 0 1 8 1 6 0 0 1 9 1 6 001 a 16 001 b 16 001 c 16 001 d 16 001 e 16 0 0 1 f 1 6 p o r t p 0 ( p 0 ) p ort p 1 (p 1 ) p o r t p 1 o u t p u t c o n t r o l r e g i s t e r ( p 1 c ) p o r t p 2 ( p 2 ) p ort p 2 di rect i on reg i ster (p 2 d) p o r t p 3 ( p 3 ) p o r t p 4 ( p 4 ) p o r t p 4 d i r e c t i o n r e g i s t e r ( p 4 d ) p ort p 5 (p 5 ) p o r t p 5 d i r e c t i o n r e g i s t e r ( p 5 d ) p o r t p 6 ( p 6 ) p o r t p 6 d i r e c t i o n r e g i s t e r ( p 6 d ) p o r t p 7 ( p 7 ) p o r t p 7 d i r e c t i o n r e g i s t e r ( p 7 d ) s er i a l i / o status reg i ster (siosts) s er i a l i / o contro l reg i ster (sio 1 con) u a r t c o n t r o l r e g i s t e r ( u a r t c o n ) b au d rate generator (brg) i n t e r r u p t c o n t r o l r e g i s t e r 2 ( i c o n 2 ) t i m e r 3 ( t 3 ) ti mer x mo d e reg i ster (txm) i n t e r r u p t e d g e s e l e c t i o n r e g i s t e r ( i n t e d g e ) c p u m o d e r e g i s t e r ( c p u m ) i nterrupt request reg i ster 1 (ireq 1 ) i nterrupt request reg i ster 2 (ireq 2 ) i n t e r r u p t c o n t r o l r e g i s t e r 1 ( i c o n 1 ) ti mer x (l ow ) (txl) t i m e r y ( l o w ) ( t y l ) ti mer 1 (t 1 ) ti mer 2 (t 2 ) t i m e r x ( h i g h ) ( t x h ) t i m e r y ( h i g h ) ( t y h ) pull reg i ster a (pulla) p u l l r e g i s t e r b ( p u l l b ) ti mer y mo d e reg i ster (tym) ti mer 123 mo d e reg i ster (t 123 m) cl oc k output contro l reg i ster (tcon) s egment output ena bl e reg i ster (seg) l c d m o d e r e g i s t e r ( l m ) a - d contro l reg i ster (adcon) a - d convers i on reg i ster (ad) t ransm i t/ r ece i ve b u ff er reg i ster (tb / rb) p o r t p 8 ( p 8 ) p ort p 8 di rect i on reg i ster (p 8 d)
single-chip 8-bit cmos microcomputer mitsubishi microcomputers 3825 group 17 i/o ports direction registers the 3825 group has 43 programmable i/o pins arranged in seven i/o ports (ports p1 6 , p1 7 , p2, p4 p6, p7 1 p7 7 , p8 0 and p8 1 ). the i/o ports have direction registers which determine the input/output direction of each individual pin. (ports p1 6 and p1 7 are shared with bits 6 and 7 of the port p1 output control register). each bit in a direction register corresponds to one pin, and each pin can be set to be input port or output port. when 0 is written to the bit corresponding to a pin, that pin be- comes an input pin. when 1 is written to that bit, that pin be- comes an output pin. if data is read from a pin set to output, the value of the port output latch is read, not the value of the pin itself. pins set to input are floating. if a pin set to input is written to, only the port output latch is written to and the pin remains floating. port p1 output control register bit 0 of the port p1 output control register (address 0003 16 ) en- ables control of the output of ports p1 0 to p1 5 . when the bit is set to 1 , the port output function is valid. in this case, setting of the pull register a to ports p1 0 to p1 5 is invalid. when resetting, bit 0 of the port p1 output control register is set to 0 (the port output function is invalid.) pull-up/pull-down control by setting the pull register a (address 0016 16 ) or the pull reg- ister b (address 0017 16 ), ports p0 to p8 except p7 0 can control ei- ther pull-down or pull-up (pins that are shared with the segment output pins for lcd are pull-down; all other pins are pull-up) with a program. however, the contents of pull register a and pull register b do not affect ports programmed as the output ports. (except for ports p0 and p3). ports p0 and p3 share the port output control function with bit 0 of the pull register a. when set to 1 , the port output function is in- valid (pull-down is valid). when set to 0 , the port output function is valid (pull-down is in- valid). the pull register a setting is invalid for pins set to segment out- put with the segment output enable register. fig. 13 structure of pull register a and pull register b p 0 , p 1 0 p 1 5 , p 3 p u l l - d o w n ( s h a r e d w i t h p 0 a n d p 3 o u t p u t c o n t r o l : r e f e r t o t h e t e x t ) p 1 6 p 1 7 p u l l - u p p 2 0 p 2 7 p u l l - u p p 8 0 , p 8 1 p u l l - u p p 4 0 p 4 3 p u l l - u p p 4 4 p 4 7 p u l l - u p n o t u s e d ( r e t u r n 0 w h e n r e a d ) pull reg i ster a (pulla : address 0016 16 ) b 7 b 0 p 5 0 p 5 3 p u l l - u p p 5 4 p 5 7 p u l l - u p p 6 0 p 6 3 p u l l - u p p 6 4 p 6 7 p u l l - u p p 7 1 p 7 3 p u l l - u p p 7 4 p 7 7 p u l l - u p n o t u s e d ( r e t u r n 0 w h e n r e a d ) 0 : d i s a b l e 1 : e n a b l e p u l l r e g i s t e r b ( p u l l b : a d d r e s s 0 0 1 7 1 6 ) b 7 b 0 n ote: th e contents o f pull reg i ster a an d pull reg i ster b do not affect ports programmed as the output port.
single-chip 8-bit cmos microcomputer mitsubishi microcomputers 3825 group 18 table 8. i/o ports functions related sfrs pull register a segment output enable register pull register a segment output enable register port p1 output control register pull register a pull register a interrupt control register 2 pull register a segment output enable register clock output control register pull register a pull register a interrupt edge selection register pull register a serial i/o control register serial i/o status register uart control register pull register b interrupt edge selection register pull register b timer x mode register pull register b timer x mode register pull register b timer y mode register pull register b timer 123 mode register pull register b a-d control register pull register b a-d control register pull register b pull register a cpu mode register lcd mode register input/output output output input/output, individual bits input/output, individual bits output input/output, individual bits input/output, individual bits input/output, individual bits input input/output, individual bits input/output, individual bits output output name port p0 port p1 port p2 port p3 port p4 port p5 port p6 port p7 port p8 common segment pin p0 0 /seg 26 p0 7 /seg 33 p1 0 /seg 34 p1 5 /seg 39 p1 6 , p1 7 p2 0 p2 7 p3 0 /seg 18 p3 7 /seg 25 p4 0 /f(x in )/ f(x in )/2, p4 1 /f(x in )/5/ f(x in )/10 p4 2 /int 0 , p4 3 /int 1 p4 4 /r x d p54/t x d p4 6 /s clk p4 7 /s rdy p5 0 /int 2 , p5 1 /int 3 p5 2 /rtp 0 , p5 3 /rtp 1 p5 4 /cntr 0 p5 5 /cntr 1 p5 6 /t out p5 7 /adt p6 0 /an 0 p6 7 /an 7 p7 0 p7 1 p7 7 p8 0 /x cout p8 1 /x cin com 0 com 3 seg 0 seg 17 non-port function lcd segment output lcd segment output key-on wake up interrupt input lcd segment output clock output external interrupt input serial i/o function i/o external interrupt input real time port function output timer x function i/o timer y function input timer 2 output a-d trigger input a-d conversion input sub-clock generating circuit i/o format cmos 3-state output cmos 3-state output cmos compatible input level cmos 3-state output cmos compatible input level cmos 3-state output cmos 3-state output cmos compatible input level cmos 3-state output cmos compatible input level cmos 3-state output cmos compatible input level cmos 3-state output cmos compatible input level cmos compatible input level cmos 3-state output cmos compatible input level cmos 3-state output lcd common output lcd segment output diagram no. (1) (1) (2) (2) (1) (2) (3) (4) (5) (6) (2) (7) (8) (9) (8) (9) (10) (11) (12) (13) (14) (15) (16) note 1: when using double-function ports as functional i/o pins, refer the method to the relevant sections. 2: make sure that the input level at each pin is either 0 v or v cc during execution of the stp instruction. when an input level is at an intermediate potential, a current will flow from v cc to v ss through the input-stage gate.
single-chip 8-bit cmos microcomputer mitsubishi microcomputers 3825 group 19 fig. 14 port block diagram (1) ( 3 ) p o r t p 4 4 p u ll -up contro l s e r i a l i / o e n a b l e b i t s er i a l i / o i nput d ata b us di rect i on register p ort l atc h ( 4 ) p ort p 4 5 p u l l - u p c o n t r o l di rect i on register d ata b us p ort l atc h s er i a l i / o outpu t p 4 5 / t x d p - c h a n n e l o u t p u t d i s a b l e b i t s er i a l i / o ena bl e bit transmission enable bi t ( 6 ) p ort p 4 7 s er i a l i / o rea d y output s e r i a l i / o m o d e s e l e c t i o n b i t s e r i a l i / o e n a b l e b i t s r d y o u t p u t e n a b l e b i t d a t a b u s p u ll -up contro l d i r e c t i o n r e g i s t e r p ort l atc h ( 7 ) p orts p 5 2 , p 5 3 r ea l t i me contro l bit p u l l - u p c o n t r o l d ata b us p o r t l a t c h d i r e c t i o n r e g i s t e r r ea l t i me port d ata ( 1 ) p o r t s p 0 , p 1 0 p 1 5 , p 3 v l 2 / v l 3 / v c c d a t a b u s p o r t l a t c h i n t e r f a c e l o g i c l e v e l s h i f t c i r c u i t p u ll - d own p ort s e g m e n t v l 1 / v s s s egment/ p ort l c d d r i v e t i m i n g p o r t / s e g m e n t s e g m e n t d a t a p o r t o n / o f f ( 2 ) p o r t s p 1 6 , p 1 7 , p 2 , p 4 0 p 4 3 , p 5 0 , p 5 1 k e y - o n w a k e u p i n t e r r u p t i n p u t i n t 0 i n t 3 i n t e r r u p t i n p u t p u ll -up contro l d ata b us p ort l atc h di rect i on register e xcept p 1 6 , p 1 7 , p 4 0 , p 4 1 ( 5 ) p ort p 4 6 s er i a l i / o ena bl e bi t s er i a l i / o c l oc k i nput p u ll -up contro l d a t a b u s s er i a l i / o c l oc k output s er i a l i / o sync h ron i zat i on c l oc k selection bit d i r e c t i o n r e g i s t e r p o r t l a t c h s er i a l i / o mo d e se l ect i on bit serial i/o enable bi t r e c e p t i o n e n a b l e b i t
single-chip 8-bit cmos microcomputer mitsubishi microcomputers 3825 group 20 fig. 15 port block diagram (2) ( 9 ) p o r t s p 5 5 , p 5 7 d ata b us p u l l - u p c o n t r o l c n t r 1 i n t e r r u p t i n p u t a - d t r i g g e r i n t e r r u p t i n p u t di rect i on register p o r t l a t c h ( 10 ) p ort p 6 d ata b us p u l l - u p c o n t r o l di rect i on register p o r t l a t c h a - d c o n v e r s i o n i n p u t a n a l o g i n p u t p i n s e l e c t i o n b i t ( 1 3 ) p o r t p 8 0 d a t a b u s p o r t x c s w i t c h b i t + p u l l - u p c o n t r o l p ort x c sw i tc h bi t o sc ill at i on c i rcu i t p ort p 8 1 p ort x c sw i tc h bi t d i r e c t i o n r e g i s t e r p o r t l a t c h ( 1 5 ) c o m 0 c o m 3 v l3 v l 2 v l 1 th e gate i nput s i gna l o f eac h transistor is controlled by the lcd duty ratio and the bia s value. v s s ( 16 ) seg 0 seg 17 t h e v o l t a g e a p p l i e d t o t h e s o u r c e s o f p - c h a n n e l a n d n - c h a n n e l t r a n s i s t o r s i s t h e c o n t r o l l e d v o l t a g e b y t h e b i a s v a l u e . v l 2 / v l 3 v l1 / v ss p u l s e o u t p u t m o d e c n t r 0 i n t e r r u p t i n p u t t i m e r o u t p u t d i r e c t i o n r e g i s t e r p o r t l a t c h d a t a b u s p 5 4 o n l y ( 1 1 ) p o r t p 7 0 ( 12 ) p orts p 7 1 p 7 7 d a t a b u s di rect i on register p o r t l a t c h ( 14 ) p ort p 8 1 d ata b us p o r t x c s w i t c h b i t s u b -c l oc k generat i ng c i rcu i t i nput d i r e c t i o n r e g i s t e r p ort l atc h p u ll -up contro l d a t a b u s p u l l - u p c o n t r o l ( 8 ) p o r t s p 5 4 , p 5 6 p o r t x c s w i t c h b i t + p u l l - u p c o n t r o l
single-chip 8-bit cmos microcomputer mitsubishi microcomputers 3825 group 21 remarks non-maskable external interrupt (active edge selectable) external interrupt (active edge selectable) valid when serial i/o is selected valid when serial i/o is selected external interrupt (active edge selectable) external interrupt (active edge selectable) external interrupt (active edge selectable) external interrupt (active edge selectable) external interrupt (valid when an ??level is applied) valid when a-d interrupt is selected non-maskable software interrupt interrupt request generating conditions at reset at detection of either rising or falling edge of int 0 input at detection of either rising or falling edge of int 1 input at completion of serial i/o data reception at completion of serial i/o transmit shift or when transmission buffer is empty at timer x underflow at timer y underflow at timer 2 underflow at timer 3 underflow at detection of either rising or falling edge of cntr 0 input at detection of either rising or falling edge of cntr 1 input at timer 1 underflow at detection of either rising or falling edge of int 2 input at detection of either rising or falling edge of int 3 input at falling of conjunction of input level for port p2 (at input mode) at falling of adt input at completion of a-d conversion at brk instruction execution valid when adt interrupt is selected external interrupt (valid at falling) notes 1 : vector addresses contain interrupt jump destination addresses. 2 : reset function in the same way as an interrupt with the highest priority. interrupts i nterrupts occur by seventeen sources: eight external, eight inter- nal, and one software. interrupt control each interrupt is controlled by an interrupt request bit, an interrupt enable bit, and the interrupt disable flag except for the software in- terrupt set by the brk instruction. an interrupt occurs if the corre- sponding interrupt request and enable bits are ??and the inter- rupt disable flag is ?? interrupt enable bits can be set or cleared by software. interrupt request bits can be cleared by software, but cannot be set by software. the brk instruction cannot be disabled with any flag or bit. the i flag disables all interrupts except the brk instruction interrupt. when several interrupts occur at the same time, the interrupts are received according to priority. interrupt operation by acceptance of an interrupt, the following operations are auto- matically performed: 1. the contents of the program counter and the processor status register are automatically pushed onto the stack. 2. the interrupt disable flag is set and the corresponding interrupt request bit is cleared. 3. the interrupt jump destination address is read from the vector table into the program counter. interrupt source reset (note 2) int 0 int 1 serial i/o reception serial i/o transmission timer x timer y timer 2 timer 3 cntr 0 cntr 1 timer 1 int 2 int 3 key input (key-on wake up) adt a-d conversion brk instruction low fffc 16 fffa 16 fff8 16 fff6 16 fff4 16 fff2 16 fff0 16 ffee 16 ffec 16 ffea 16 ffe8 16 ffe6 16 ffe4 16 ffe2 16 ffe0 16 ffde 16 ffdc 16 high fffd 16 fffb 16 fff9 16 fff7 16 fff5 16 fff3 16 fff1 16 ffef 16 ffed 16 ffeb 16 ffe9 16 ffe7 16 ffe5 16 ffe3 16 ffe1 16 ffdf 16 ffdd 16 table 9. interrupt vector addresses and priority priority 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 vector addresses (note 1)
single-chip 8-bit cmos microcomputer mitsubishi microcomputers 3825 group 22 fig. 16 interrupt control fig. 17 structure of interrupt-related registers i n t e r r u p t r e q u e s t b i t i n t e r r u p t e n a b l e b i t i n t e r r u p t d i s a b l e f l a g ( i ) b r k i n s t r u c t i o n r e s e t i n t e r r u p t r e q u e s t b 7 b 0 i n t e r r u p t e d g e s e l e c t i o n r e g i s t e r i n t 0 i n t e r r u p t e d g e s e l e c t i o n b i t i n t 1 i n t e r r u p t e d g e s e l e c t i o n b i t i n t 2 i n t e r r u p t e d g e s e l e c t i o n b i t i n t 3 i n t e r r u p t e d g e s e l e c t i o n b i t n o t u s e d ( r e t u r n 0 w h e n r e a d ) (intedge : a dd ress 003 a 16 ) i n t e r r u p t r e q u e s t r e g i s t e r 1 i n t 0 i n t e r r u p t r e q u e s t b i t i n t 1 i n t e r r u p t r e q u e s t b i t s e r i a l i / o r e c e i v e i n t e r r u p t r e q u e s t b i t s e r i a l i / o t r a n s m i t i n t e r r u p t r e q u e s t b i t t i m e r x i n t e r r u p t r e q u e s t b i t t i m e r y i n t e r r u p t r e q u e s t b i t t i m e r 2 i n t e r r u p t r e q u e s t b i t t i m e r 3 i n t e r r u p t r e q u e s t b i t i n t e r r u p t c o n t r o l r e g i s t e r 1 i n t 0 i n t e r r u p t e n a b l e b i t i n t 1 i n t e r r u p t e n a b l e b i t s e r i a l i / o r e c e i v e i n t e r r u p t e n a b l e b i t s e r i a l i / o t r a n s m i t i n t e r r u p t e n a b l e b i t t i m e r x i n t e r r u p t e n a b l e b i t t i m e r y i n t e r r u p t e n a b l e b i t t i m e r 2 i n t e r r u p t e n a b l e b i t t i m e r 3 i n t e r r u p t e n a b l e b i t 0 : n o i n t e r r u p t r e q u e s t i s s u e d 1 : i n t e r r u p t r e q u e s t i s s u e d ( i r e q 1 : a d d r e s s 0 0 3 c 1 6 ) ( i c o n 1 : a d d r e s s 0 0 3 e 1 6 ) i n t e r r u p t r e q u e s t r e g i s t e r 2 cntr 0 i nterrupt request bi t cntr 1 interrupt request bit timer 1 interrupt request bit int 2 interrupt request bit int 3 interrupt request bit key input interrupt request bit adt/ad conversion interrupt request bit not used (returns 0 when read) ( i r e q 2 : a d d r e s s 0 0 3 d 1 6 ) i nterrupt contro l reg i ster 2 c n t r 0 i n t e r r u p t e n a b l e b i t c n t r 1 i n t e r r u p t e n a b l e b i t t i m e r 1 i n t e r r u p t e n a b l e b i t i n t 2 i n t e r r u p t e n a b l e b i t i n t 3 i n t e r r u p t e n a b l e b i t k e y i n p u t i n t e r r u p t e n a b l e b i t a d t / a d c o n v e r s i o n i n t e r r u p t e n a b l e b i t n o t u s e d ( r e t u r n s 0 w h e n r e a d ) ( d o n o t w r i t e 1 t o t h i s b i t ) 0 : i n t e r r u p t s d i s a b l e d 1 : i n t e r r u p t s e n a b l e d (icon 2 : a dd ress 003 f 16 ) 0 : f a l l i n g e d g e a c t i v e 1 : r i s i n g e d g e a c t i v e b 7 b 0 b 7 b 0 b 7 b 0 b 7 b 0 notes on interrupts when setting the followings, the interrupt request bit may be set to 1 . when setting external interrupt active edge related register: interrupt edge selection register (address 3a 16 ) timer x mode register (address 27 16 ) timer y mode register (address 28 16 ) when switching interrupt sources of an interrupt vector address where two or more interrupt sources are allocated related register: a-d control regsiter (address 34 16 ) when not requiring for the interrupt occurrence synchronized with these setting, take the following sequence. ? set the corresponding interrupt enable bit to 0 (disabled). ? set the interrupt edge select bit or the interrupt source select bit to 1 . ? set the corresponding interrupt request bit to 0 after 1 or more instructions have been executed. ? set the corresponding interrupt enable bit to 1 (enabled).
single-chip 8-bit cmos microcomputer mitsubishi microcomputers 3825 group 23 key input interrupt (key-on wake up) a key-on wake up interrupt request is generated by applying a falling edge to any pin of port p2 that have been set to input mode. in other words, it is generated when and of input level goes from 1 to 0 . an example of using a key input interrupt is shown in figure 18, where an interrupt request is generated by pressing one of the keys consisted as an active-low key matrix which inputs to ports p2 0 p2 3 . fig. 18 connection example when using key input interrupt and port p2 block diagram ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? p o r t p 2 0 l a t c h port p2 0 direction register = 0 p o r t p 2 1 l a t c h port p2 1 direction register = 0 port p2 2 latch port p2 2 direction register = 0 p o r t p 2 3 l a t c h port p2 3 direction register = 0 port p2 4 latch port p2 4 direction register = 1 port p2 5 latch port p2 5 direction register = 1 p o r t p 2 6 l a t c h p o r t p 2 6 d i r e c t i o n r e g i s t e r = 1 p o r t p 2 7 l a t c h p o r t p 2 7 d i r e c t i o n r e g i s t e r = 1 p 2 0 i n p u t p2 1 input p 2 2 i n p u t p2 3 input p2 4 output p2 5 output p 2 6 o u t p u t p2 7 output p u l l r e g i s t e r a b i t 2 = 1 port p2 input reading circuit p o r t p x x l l e v e l o u t p u t ? p - c h a n n e l t r a n s i s t o r f o r p u l l - u p ? ? c m o s o u t p u t b u f f e r k e y i n p u t i n t e r r u p t r e q u e s t
single-chip 8-bit cmos microcomputer mitsubishi microcomputers 3825 group 24 timers the 3825 group has five timers: timer x, timer y, timer 1, timer 2, and timer 3. timer x and timer y are 16-bit timers, and timer 1, timer 2, and timer 3 are 8-bit timers. all timers are down count timers. when the timer reaches ?0 16 ? an underflow occurs at the next count pulse and the correspond- ing timer latch is reloaded into the timer and the count is contin- ued. when a timer underflows, the interrupt request bit corre- sponding to that timer is set to ?? read and write operation on 16-bit timer must be performed for both high- and low-order bytes. when reading a 16-bit timer, read the high-order byte first. when writing to a 16-bit timer, write the low-order byte first. the 16-bit timer cannot perform the correct op- eration when reading during the write operation, or when writing during the read operation. fig. 19 timer block diagram cntr 0 act i ve edge switch bit t i m e r 1 c o u n t s o u r c e s e l e c t i o n b i t r ea l t i me port control bit 0 1 p 5 5 / cntr 1 0 f(x in ) /16 ( f ( x cin ) /16 in low-s p eed mode ] ) c n t r 1 a c t i v e e d g e s w i t c h b i t 10 ti mer y stop control bi t falling edge detection p er i o d measurement mode ti mer y interrupt request pulse width hl continuously measurement mode rising edge detection 0 0 , 0 1 , 1 1 t i m e r y o p e r a t i n g m o d e b i t s ti mer x interrupt request ti mer x mo d e reg i ster write signal p 5 4 / c n t r 0 q q t s p 5 4 d i r e c t i o n r e g i s t e r p u l se output mo d e p 5 4 l atc h t i m e r x s t o p c o n t r o l b i t 0 1 t i m e r x w r i t e c o n t r o l b i t q d l a t c h q d l a t c h 1 0 1 1 0 timer x operat- ing mode bits 00 , 01 , 11 f ( x i n ) / 1 6 ( f ( x c i n ) / 1 6 i n l o w - s p e e d m o d e ? ) p u l se w id t h measurement mode c n t r 0 a c t i v e e d g e s w i t c h b i t p u l se output mo d e q q t s 0 p 5 6 di rect i on reg i ster p 5 6 l a t c h 1 t o u t o u t p u t a c t i v e e d g e s w i t c h b i t 0 t i m e r 2 w r i t e c o n t r o l b i t 0 1 t out output control bit 1 p 5 6 / t o u t x cin t i m e r 3 c o u n t s o u r c e s e l e c t i o n b i t 0 1 ti mer 2 interrupt request ti mer 3 interrupt request t o u t o u t p u t c o n t r o l b i t ti mer 2 count source selection bit ti mer 1 interrupt request d a t a b u s f ( x i n ) / 1 6 ( f ( x c i n ) / 1 6 i n l o w - s p e e d m o d e ] ) f(x in )/16 ( f ( x cin ) /16 in low-s p eed mode ] ) f ( x in ) /16 ( f ( x cin ) /16 in low-s p eed mode ] ) ? internal clock 00 , 01 , 10 11 p 5 2 di rect i on reg i ster 0 r e a l t i m e p o r t c o n t r o l b i t 1 p 5 2 p 5 2 l a t c h p 5 3 d i r e c t i o n r e g i s t e r 0 r ea l t i me port control bit 1 p 5 3 p 5 3 l a t c h p 5 2 d a t a f o r r e a l t i m e p o r t p 5 3 d ata f or rea l t i me port timer y (low) (8) timer y (high) (8) ti mer 3 l atc h ( 8 ) ti mer 3 ( 8 ) t i m e r 1 l a t c h ( 8 ) ti mer 1 ( 8 ) t i m e r 2 l a t c h ( 8 ) ti mer 2 ( 8 ) t i m e r x ( l o w ) ( 8 ) t i m e r x ( h i g h ) ( 8 ) t i m e r x ( l o w ) l a t c h ( 8 )t i m e r x ( h i g h ) l a t c h ( 8 ) timer y (low) latch (8) timer y (high) latch (8)
single-chip 8-bit cmos microcomputer mitsubishi microcomputers 3825 group 25 timer x timer x is a 16-bit timer that can be selected in one of four modes and can be controlled the timer x write and the real time port by setting the timer x mode register. (1) timer mode the timer counts f(x in )/16 (or f(x cin )/16 in low-speed mode). (2) pulse output mode each time the timer underflows, a signal output from the cntr 0 pin is inverted. except for this, the operation in pulse output mode is the same as in timer mode. when using a timer in this mode, set the corresponding port p5 4 direction register to output mode. (3) event counter mode the timer counts signals input through the cntr 0 pin. except for this, the operation in event counter mode is the same as in timer mode. when using a timer in this mode, set the corre- sponding port p5 4 direction register to input mode. (4) pulse width measurement mode the count source is f(x in )/16 (or f(x cin )/16 in low-speed mode). if cntr 0 active edge switch bit is 0 , the timer counts while the in- put signal of cntr 0 pin is at h . if it is 1 , the timer counts while the input signal of cntr 0 pin is at l . when using a timer in this mode, set the corresponding port p5 4 direction register to input mode. timer x write control if the timer x write control bit is 0 , when the value is written in the address of timer x, the value is loaded in the timer x and the latch at the same time. if the timer x write control bit is 1 , when the value is written in the address of timer x, the value is loaded only in the latch. the value in the latch is loaded in timer x after timer x underflows. if the value is written in latch only, unexpected value may be set in the high-order counter when the writing in high-order latch and the underflow of timer x are performed at the same timing. real time port control while the real time port function is valid, data for the real time port are output from ports p5 2 and p5 3 each time the timer x underflows. (however, if the real time port control bit is changed from 0 to 1 after set of the real time port data, data are output independent of the timer x operation.) if the data for the real time port is changed while the real time port function is valid, the changed data are output at the next underflow of timer x. before using this function, set the corresponding port direction registers to output mode. note on cntr 0 interrupt active edge selection cntr 0 interrupt active edge depends on the cntr 0 active edge switch bit. fig. 20 structure of timer x mode register t i m e r x m o d e r e g i s t e r ( t x m : a d d r e s s 0 0 2 7 1 6 ) t i m e r x w r i t e c o n t r o l b i t 0 : w r i t e v a l u e i n l a t c h a n d c o u n t e r 1 : w r i t e v a l u e i n l a t c h o n l y r e a l t i m e p o r t c o n t r o l b i t 0 : r e a l t i m e p o r t f u n c t i o n i n v a l i d 1 : r e a l t i m e p o r t f u n c t i o n v a l i d p 5 2 d a t a f o r r e a l t i m e p o r t p 5 3 d a t a f o r r e a l t i m e p o r t t i m e r x o p e r a t i n g m o d e b i t s b 5 b 4 00 : t i m e r m o d e 01 : p u l s e o u t p u t m o d e 10 : e v e n t c o u n t e r m o d e 11 : p u l s e w i d t h m e a s u r e m e n t m o d e c n t r 0 a c t i v e e d g e s w i t c h b i t 0 : c o u n t a t r i s i n g e d g e i n e v e n t c o u n t e r m o d e s t a r t f r o m h o u t p u t i n p u l s e o u t p u t m o d e m e a s u r e h p u l s e w i d t h i n p u l s e w i d t h m e a s u r e m e n t m o d e f a l l i n g e d g e a c t i v e f o r c n t r 0 i n t e r r u p t 1 : c o u n t a t f a l l i n g e d g e i n e v e n t c o u n t e r m o d e s t a r t f r o m l o u t p u t i n p u l s e o u t p u t m o d e m e a s u r e l p u l s e w i d t h i n p u l s e w i d t h m e a s u r e m e n t m o d e r i s i n g e d g e a c t i v e f o r c n t r 0 i n t e r r u p t t i m e r x s t o p c o n t r o l b i t 0 : c o u n t s t a r t 1 : c o u n t s t o p b 7 b 0
single-chip 8-bit cmos microcomputer mitsubishi microcomputers 3825 group 26 timer y timer y is a 16-bit timer that can be selected in one of four modes. (1) timer mode the timer counts f(x in )/16 (or f(x cin )/16 in low-speed mode). (2) period measurement mode cntr 1 interrupt request is generated at rising/falling edge of cntr 1 pin input signal. simultaneously, the value in timer y latch is reloaded in timer y and timer y continues counting down. ex- cept for the above-mentioned, the operation in period measure- ment mode is the same as in timer mode. the timer value just before the reloading at rising/falling of cntr 1 pin input signal is retained until the timer y is read once after the reload. the rising/falling timing of cntr 1 pin input signal is found by cntr 1 interrupt. when using a timer in this mode, set the corre- sponding port p5 5 direction register to input mode. (3) event counter mode the timer counts signals input through the cntr 1 pin. except for this, the operation in event counter mode is the same as in timer mode. when using a timer in this mode, set the corre- sponding port p5 5 direction register to input mode. (4) pulse width hl continuously measure- ment mode cntr 1 interrupt request is generated at both rising and falling edges of cntr 1 pin input signal. except for this, the operation in pulse width hl continuously measurement mode is the same as in period measurement mode. when using a timer in this mode, set the corresponding port p5 5 direction register to input mode. note on cntr 1 interrupt active edge selection cntr 1 interrupt active edge depends on the cntr 1 active edge switch bit. however, in pulse width hl continuously measurement mode, cntr 1 interrupt request is generated at both rising and falling edges of cntr 1 pin input signal regardless of the setting of cntr 1 active edge switch bit. fig. 21 structure of timer y mode register t i m e r y m o d e r e g i s t e r ( t y m : a d d r e s s 0 0 2 8 1 6 ) b 7 b 0 not used (return 0 when read) timer y operating mode bits b5 b4 0 0 : timer mode 0 1 : period measurement mode 1 0 : event counter mode 1 1 : pulse width hl continuously measurement mode cntr 1 active edge switch bit 0 : count at rising edge in event counter mode measure the falling edge to falling edge period in period measurement mode falling edge active for cntr 1 interrupt 1 : count at falling edge in event counter mode measure the rising edge period in period measurement mode rising edge active for cntr 1 interrupt timer y stop control bit 0 : count start 1 : count stop
single-chip 8-bit cmos microcomputer mitsubishi microcomputers 3825 group 27 timer 1, timer 2, timer 3 timer 1, timer 2, and timer 3 are 8-bit timers. the count source for each timer can be selected by timer 123 mode register. the timer latch value is not affected by a change of the count source. how- ever, because changing the count source may cause an inadvert- ent count down of the timer. therefore, rewrite the value of timer whenever the count source is changed. timer 2 write control if the timer 2 write control bit is 0 , when the value is written in the address of timer 2, the value is loaded in the timer 2 and the latch at the same time. if the timer 2 write control bit is 1 , when the value is written in the address of timer 2, the value is loaded only in the latch. the value in the latch is loaded in timer 2 after timer 2 underflows. timer 2 output control when the timer 2 (t out ) is output enabled, an inversion signal from pin t out is output each time timer 2 underflows. in this case, set the port p5 6 shared with the port t out to the out- put mode. note on timer 1 to timer 3 when the count source of timers 1 to 3 is changed, the timer counting value may be changed large because a thin pulse is gen- erated in count input of timer. if timer 1 output is selected as the count source of timer 2 or timer 3, when timer 1 is written, the counting value of timer 2 or timer 3 may be changed large be- cause a thin pulse is generated in timer 1 output. therefore, set the value of timer in the order of timer 1, timer 2 and timer 3 after the count source selection of timer 1 to 3. fig. 22 structure of timer 123 mode register t out output act i ve e d ge sw i tc h bi t 0 : start at h output 1 : start at l output t out output control bit 0 : t out output disabled 1 : t out output enabled timer 2 write control bit 0 : write data in latch and counter 1 : write data in latch only timer 2 count source selection bit 0 : timer 1 output 1 : f(x in )/16 (or f(x cin )/16 in low-speed mode) timer 3 count source selection bit 0 : timer 1 output 1 : f(x in )/16 (or f(x cin )/16 in low-speed mode) timer 1 count source selection bit 0 : f(x in )/16 (or f(x cin )/16 in low-speed mode) 1 : f(x cin ) not used (return 0 when read) t i m e r 1 2 3 m o d e r e g i s t e r ( t 1 2 3 m : a d d r e s s 0 0 2 9 1 6 ) n o t e : i n t e r n a l c l o c k i s f ( x c i n ) / 2 i n t h e l o w - s p e e d m o d e . b 7 b 0
single-chip 8-bit cmos microcomputer mitsubishi microcomputers 3825 group 28 serial i/o serial i/o can be used as either clock synchronous or asynchro- nous (uart) serial i/o. a dedicated timer (baud rate generator) is also provided for baud rate generation. (1) clock synchronous serial i/o mode clock synchronous serial i/o mode can be selected by setting the mode selection bit of the serial i/o control register to 1 . for clock synchronous serial i/o, the transmitter and the receiver must use the same clock. if an internal clock is used, transfer is started by a write signal to the tb/rb (address 0018 16 ). fig. 23 block diagram of clock synchronous serial i/o fig. 24 operation of clock synchronous serial i/o function p 4 6 / s c l k p 4 7 / s r d y p 4 4 / r x d p 4 5 / t x d f ( x i n ) 1 / 4 1/4 f / f s e r i a l i / o s t a t u s r e g i s t e r serial i/o control register r e c e i v e b u f f e r r e g i s t e r a d d r e s s 0 0 1 8 1 6 receive shift register r ece i ve b u ff er f u ll fl ag (rbf) r e c e i v e i n t e r r u p t r e q u e s t ( r i ) clock control circuit s h i f t c l o c k s er i a l i / o sync h ron i zat i on clock selection bit frequency division ratio 1/(n+1) b a u d r a t e g e n e r a t o r add ress 001 c 16 brg count source se l ect i on bi t clock control circuit f a l l i n g - e d g e d e t e c t o r d ata b us add ress 0018 16 s h i f t c l o c k t ransm i t s hif t reg i ster s hif t comp l et i on fl ag (tsc) t ransm i t b u ff er empty fl ag (tbe) t ransm i t i nterrupt request (ti) t ransm i t i nterrupt source se l ect i on bi t a d d r e s s 0 0 1 9 1 6 d ata b us a d d r e s s 0 0 1 a 1 6 t r a n s m i t b u f f e r r e g i s t e r ( t b ) t r a n s m i t s h i f t r e g i s t e r ( f ( x c i n ) i n l o w - s p e e d m o d e ) r e c e i v e e n a b l e s i g n a l s r d y d 7 d 0 d 1 d 2 d 3 d 4 d 5 d 6 rbf = 1 tsc = 1 t b e = 0 tbe = 1 tsc = 0 t r a n s f e r s h i f t c l o c k ( 1 / 2 t o 1 / 2 0 4 8 o f t h e i n t e r n a l c l o c k , o r a n e x t e r n a l c l o c k ) s er i a l output t x d s e r i a l i n p u t r x d w r i t e s i g n a l t o r e c e i v e / t r a n s m i t b u f f e r r e g i s t e r ( a d d r e s s 0 0 1 8 1 6 ) o verrun error (oe) detection n o t e s 1 : t h e t r a n s m i t i n t e r r u p t ( t i ) c a n b e g e n e r a t e d e i t h e r w h e n t h e t r a n s m i t b u f f e r r e g i s t e r h a s e m p t i e d ( t b e = 1 ) o r a f t e r t h e t r a n s m i t s h i f t o p e r a t i o n h a s e n d e d ( t s c = 1 ) , b y s e t t i n g t h e t r a n s m i t i n t e r r u p t s o u r c e s e l e c t i o n b i t ( t i c ) o f t h e s e r i a l i / o c o n t r o l r e g i s t e r . 2 : i f d a t a i s w r i t t e n t o t h e t r a n s m i t b u f f e r r e g i s t e r w h e n t s c = 0 , t h e t r a n s m i t c l o c k i s g e n e r a t e d c o n t i n u o u s l y a n d s e r i a l d a t a i s o u t p u t c o n t i n u o u s l y f r o m t h e t x d p i n . 3 : t h e r e c e i v e i n t e r r u p t ( r i ) i s s e t w h e n t h e r e c e i v e b u f f e r f u l l f l a g ( r b f ) b e c o m e s 1 . d 7 d 0 d 1 d 2 d 3 d 4 d 5 d 6
single-chip 8-bit cmos microcomputer mitsubishi microcomputers 3825 group 29 (2) asynchronous serial i/o (uart) mode clock asynchronous serial i/o mode (uart) can be selected by clearing the serial i/o mode selection bit of the serial i/o control register to 0 . eight serial data transfer formats can be selected, and the transfer formats used by a transmitter and receiver must be identical. the transmit and receive shift registers each have a buffer regis- ter, but the two buffers have the same address in memory. since the shift register cannot be written to or read from directly, transmit data is written to the transmit buffer, and receive data is read from the receive buffer. the transmit buffer can also hold the next data to be transmitted, and the receive buffer register can hold a character while the next character is being received. fig. 25 block diagram of uart serial i/o fig. 26 operation of uart serial i/o function f(x in ) 1 / 4 o e p e f e 1/16 1/16 d ata b us r e c e i v e b u f f e r r e g i s t e r a d d r e s s 0 0 1 8 1 6 r e c e i v e s h i f t r e g i s t e r r e c e i v e b u f f e r f u l l f l a g ( r b f ) r e c e i v e i n t e r r u p t r e q u e s t ( r i ) b au d rate generator f requency di v i s i on rat i o 1/ ( n+1 ) add ress 001 c 16 st/sp/pa generator transmit buffer register d ata b us t r a n s m i t s h i f t r e g i s t e r add ress 0018 16 t ransm i t s hif t reg i ster s hif t comp l et i on fl ag (tsc) t ransm i t b u ff er empty fl ag (tbe) t ransm i t i nterrupt request (ti) add ress 0019 16 s t d e t e c t o r s p d e t e c t o r u a r t c o n t r o l r e g i s t e r add ress 001 b 16 c h a r a c t e r l e n g t h s e l e c t i o n b i t a d d r e s s 0 0 1 a 1 6 b r g c o u n t s o u r c e s e l e c t i o n b i t t ransm i t i nterrupt source se l ect i on bit s er i a l i / o sync h ron i zat i on c l oc k se l ect i on bi t c l o c k c o n t r o l c i r c u i t c h a r a c t e r l e n g t h s e l e c t i o n b i t 7 b i t s 8 b i t s s e r i a l i / o c o n t r o l r e g i s t e r p 4 6 / s c l k s er i a l i / o status reg i ster p 4 4 / r x d p 4 5 / t x d ( f ( x c i n ) i n l o w - s p e e d m o d e ) t s c = 0 t b e = 1 rbf =0 t b e = 0 tbe =0 r b f = 1 r b f = 1 s t d 0 d 1 s p d 0 d 1 s t sp tbe =1 tsc=1 ? st d 0 d 1 sp d 0 d 1 st s p t r a n s m i t b u f f e r w r i t e s i g n a l ? generated at 2nd bit in 2-stop-bit mode 1 s t a r t b i t 7 o r 8 d a t a b i t s 1 o r 0 p a r i t y b i t 1 o r 2 s t o p b i t ( s ) 1 : e r r o r f l a g d e t e c t i o n o c c u r s a t t h e s a m e t i m e t h a t t h e r b f f l a g b e c o m e s 1 ( a t 1 s t s t o p b i t , d u r i n g r e c e p t i o n ) . 2 : t h e t r a n s m i t i n t e r r u p t ( t i ) c a n b e g e n e r a t e d t o o c c u r w h e n e i t h e r t h e t b e o r t s c f l a g b e c o m e s 1 , d e p e n d i n g o n t h e s e t t i n g o f t h e t r a n s m i t i n t e r r u p t s o u r c e s e l e c t i o n b i t ( t i c ) o f t h e s e r i a l i / o c o n t r o l r e g i s t e r . 3 : t h e r e c e i v e i n t e r r u p t ( r i ) i s s e t w h e n t h e r b f f l a g b e c o m e s 1 . 4 : a f t e r d a t a i s w r i t t e n t o t h e t r a n s m i t b u f f e r r e g i s t e r w h e n t s c = 1 , 0 . 5 t o 1 . 5 c y c l e s o f t h e d a t a s h i f t c y c l e i s n e c e s s a r y u n t i l c h a n g i n g t o t s c = 0 . n o t e s s er i a l output t x d s e r i a l i n p u t r x d r e c e i v e b u f f e r r e a d s i g n a l t r a n s m i t o r r e c e i v e c l o c k
single-chip 8-bit cmos microcomputer mitsubishi microcomputers 3825 group 30 [transmit buffer/receive buffer register (tb/ rb)] 0018 16 the transmit buffer register and the receive buffer register are lo- cated at the same address. the transmit buffer register is write- only and the receive buffer register is read-only. if a character bit length is 7 bits, the msb of data stored in the receive buffer regis- ter is ?? [serial i/o status register (siosts)] 0019 16 the read-only serial i/o status register consists of seven flags (bits 0 to 6) which indicate the operating status of the serial i/o function and various errors. three of the flags (bits 4 to 6) are valid only in uart mode. the receive buffer full flag (bit 1) is cleared to ??when the receive buffer is read. if there is an error, it is detected at the same time that data is transferred from the receive shift register to the receive buffer reg- ister, and the receive buffer full flag is set. a write to the serial i/o status register clears all the error flags oe, pe, fe, and se (bit 3 to bit 6, respectively). writing ??to the serial i/o enable bit sioe (bit 7 of the serial i/o control register) also clears all the status flags, including the error flags. all bits of the serial i/o status register are initialized to ??at reset, but if the transmit enable bit (bit 4) of the serial i/o control register has been set to ?? the transmit shift register shift completion flag (bit 2) and the transmit buffer empty flag (bit 0) become ?? [serial i/o control register (siocon)] 001a 16 the serial i/o control register contains eight control bits for the se- rial i/o function. [uart control register (uartcon)] 001b 16 the uart control register consists of four control bits (bits 0 to 3) which are valid when asynchronous serial i/o is selected and set the data format of an data transfer. one bit in this register (bit 4) is always valid and sets the output structure of the p4 5 /t x d pin. [baud rate generator (brg)] 001c 16 the baud rate generator determines the baud rate for serial trans- fer. the baud rate generator divides the frequency of the count source by 1/(n + 1), where n is the value written to the baud rate genera- tor. notes on serial i/o when setting the transmit enable bit to ?? the serial i/o transmit interrupt request bit is automatically set to ?? when not requiring the interrupt occurrence synchronized with the transmission enalbed, take the following sequence. ? set the serial i/o transmit interrupt enable bit to ??(disabled). ? set the transmit enable bit to ?? ? set the serial i/o transmit interrupt request bit to ??after 1 or more instructions have been executed. ? set the serial i/o transmit interrupt enable bit to ??(enabled).
single-chip 8-bit cmos microcomputer mitsubishi microcomputers 3825 group 31 fig. 27 structure of serial i/o control registers b r g c o u n t s o u r c e s e l e c t i o n b i t ( c s s ) 0 : f ( x i n ) ( f ( x c i n ) i n l o w - s p e e d m o d e ) 1 : f ( x i n ) / 4 ( f ( x c i n ) / 4 i n l o w - s p e e d m o d e ) s e r i a l i / o s y n c h r o n i z a t i o n c l o c k s e l e c t i o n b i t ( s c s ) 0 : b r g o u t p u t d i v i d e d b y 4 w h e n c l o c k s y n c h r o n i z e d s e r i a l i / o i s s e l e c t e d . b r g o u t p u t d i v i d e d b y 1 6 w h e n u a r t i s s e l e c t e d . 1 : e x t e r n a l c l o c k i n p u t w h e n c l o c k s y n c h r o n i z e d s e r i a l i / o i s s e l e c t e d . e x t e r n a l c l o c k i n p u t d i v i d e d b y 1 6 w h e n u a r t i s s e l e c t e d . s r d y o u t p u t e n a b l e b i t ( s r d y ) 0 : p 4 7 p i n o p e r a t e s a s o r d i n a r y i / o p i n 1 : p 4 7 p i n o p e r a t e s a s s r d y o u t p u t p i n t r a n s m i t i n t e r r u p t s o u r c e s e l e c t i o n b i t ( t i c ) 0 : i n t e r r u p t w h e n t r a n s m i t b u f f e r h a s e m p t i e d 1 : i n t e r r u p t w h e n t r a n s m i t s h i f t o p e r a t i o n i s c o m p l e t e d t r a n s m i t e n a b l e b i t ( t e ) 0 : t r a n s m i t d i s a b l e d 1 : t r a n s m i t e n a b l e d r e c e i v e e n a b l e b i t ( r e ) 0 : r e c e i v e d i s a b l e d 1 : r e c e i v e e n a b l e d s e r i a l i / o m o d e s e l e c t i o n b i t ( s i o m ) 0 : a s y n c h r o n o u s s e r i a l i / o ( u a r t ) 1 : c l o c k s y n c h r o n o u s s e r i a l i / o s e r i a l i / o e n a b l e b i t ( s i o e ) 0 : s e r i a l i / o d i s a b l e d ( p i n s p 4 4 p 4 7 o p e r a t e a s o r d i n a r y i / o p i n s ) 1 : s e r i a l i / o e n a b l e d ( p i n s p 4 4 p 4 7 o p e r a t e a s s e r i a l i / o p i n s ) s er i a l i / o contro l reg i ster (siocon : address 001a 16 ) b7 b0 t r a n s m i t b u f f e r e m p t y f l a g ( t b e ) 0 : b u f f e r f u l l 1 : b u f f e r e m p t y r e c e i v e b u f f e r f u l l f l a g ( r b f ) 0 : b u f f e r e m p t y 1 : b u f f e r f u l l t r a n s m i t s h i f t r e g i s t e r s h i f t c o m p l e t i o n f l a g ( t s c ) 0 : t r a n s m i t s h i f t i n p r o g r e s s 1 : t r a n s m i t s h i f t c o m p l e t e d o v e r r u n e r r o r f l a g ( o e ) 0 : n o e r r o r 1 : o v e r r u n e r r o r p a r i t y e r r o r f l a g ( p e ) 0 : n o e r r o r 1 : p a r i t y e r r o r f r a m i n g e r r o r f l a g ( f e ) 0 : n o e r r o r 1 : f r a m i n g e r r o r s u m m i n g e r r o r f l a g ( s e ) 0 : ( o e ) u ( p e ) u ( f e ) = 0 1 : ( o e ) u ( p e ) u ( f e ) = 1 n o t u s e d ( r e t u r n s 1 w h e n r e a d ) s e r i a l i / o s t a t u s r e g i s t e r ( s i o s t s : a d d r e s s 0 0 1 9 1 6 ) b7 b0 u a r t c o n t r o l r e g i s t e r ( u a r t c o n : a d d r e s s 0 0 1 b 1 6 ) ch aracter l engt h se l ect i on bi t (chas) 0: 8 bits 1: 7 bits parity enable bit (pare) 0: parity checking disabled 1: parity checking enabled parity selection bit (pars) 0: even parity 1: odd parity stop bit length selection bit (stps) 0: 1 stop bit 1: 2 stop bits p4 5 /t x d p-channel output disable bit (poff) 0: cmos output (in output mode) 1: n-channel open-drain output (in output mode) not used (return 1 when read) b7 b0
single-chip 8-bit cmos microcomputer mitsubishi microcomputers 3825 group 32 a-d converter the functional blocks of the a-d converter are described below. [a-d conversion register (ad)] 0035 16 the a-d conversion register is a read-only register that contains the result of an a-d conversion. when reading this register during an a-d conversion, the previous conversion result is read. [a-d control register (adcon)] 0034 16 the a-d control register controls the a-d conversion process. bits 0 to 2 of this register select specific analog input pins. bit 3 signals the completion of an a-d conversion. the value of this bit remains at 0 during an a-d conversion, then changes to 1 when the a- d conversion is completed. writing 0 to this bit starts the a-d conversion. bit 4 controls the transistor which breaks the through current of the resistor ladder. when bit 5, which is the ad external trigger valid bit, is set to 1 , this bit enables a-d conversion even by a falling edge of an adt input. set ports which share with adt pins to input when using an a-d external trigger. comparison voltage generator the comparison voltage generator divides the voltage between av ss and v ref by 256, and outputs the divided voltages. channel selector the channel selector selects one of the input ports p6 7 /an 7 p6 0 / an 0 . comparator and control circuit the comparator and control circuit compare an analog input volt- age with the comparison voltage and store the result in the a-d conversion register. when an a-d conversion is completed, the control circuit sets the ad conversion completion bit and the ad interrupt request bit to 1 . note that the comparator is constructed linked to a capacitor, so set f(x in ) to at least 500khz during a-d conversion. use the clock divided from the main clock x in as the internal clock . fig. 29 a-d converter block diagram fig. 28 structure of a-d control register a - d c o n t r o l r e g i s t e r ( a d c o n : a d d r e s s 0 0 3 4 1 6 ) a d c o n v e r s i o n c o m p l e t i o n b i t 0 : c o n v e r s i o n i n p r o g r e s s 1 : c o n v e r s i o n c o m p l e t e d a n a l o g i n p u t p i n s e l e c t i o n b i t s 0 0 0 : p 6 0 / a n 0 0 0 1 : p 6 1 / a n 1 0 1 0 : p 6 2 / a n 2 0 1 1 : p 6 3 / a n 3 1 0 0 : p 6 4 / a n 4 1 0 1 : p 6 5 / a n 5 1 1 0 : p 6 6 / a n 6 1 1 1 : p 6 7 / a n 7 v r e f i n p u t s w i t c h b i t 0 : o f f 1 : o n a d e x t e r n a l t r i g g e r v a l i d b i t 0 : a - d e x t e r n a l t r i g g e r i n v a l i d 1 : a - d e x t e r n a l t r i g g e r v a l i d b 7 b 0 i n t e r r u p t s o u r c e s e l e c t i o n b i t 0 : i n t e r r u p t r e q u e s t a t a - d c o n v e r s i o n c o m p l e t e d 1 : i n t e r r u p t r e q u e s t a t a d t i n p u t f a l l i n g n o t u s e d ( r e t u r n s 0 w h e n r e a d ) c o m p a r a t o r a - d c o n t r o l c i r c u i t a d t / a - d i n t e r r u p t r e q u e s t av s s v r e f p 6 0 / a n 0 d a t a b u s a - d c o n t r o l r e g i s t e r b 7 b 0 a - d convers i on register r es i stor l a dd e r c h a n n e l s e l e c t o r p 6 7 / a n 7 p 6 6 / a n 6 p 6 5 / a n 5 p 6 4 / a n 4 p 6 3 / a n 3 p 6 2 / a n 2 p 6 1 / a n 1 p 5 7 / a d t 8 3
single-chip 8-bit cmos microcomputer mitsubishi microcomputers 3825 group 33 lcd drive control circuit the 3825 group has the built-in liquid crystal display (lcd) drive control circuit consisting of the following. lcd display ram segment output enable register lcd mode register voltage multiplier selector timing controller common driver segment driver bias control circuit a maximum of 40 segment output pins and 4 common output pins can be used. up to 160 pixels can be controlled for lcd display. when the lcd fig. 30 structure of segment output enable register and lcd mode register enable bit is set to 1 after data is set in the lcd mode register, the segment output enable register and the lcd display ram, the lcd drive control circuit starts reading the display data automati- cally, performs the bias control and the duty ratio control, and dis- plays the data on the lcd panel. table 10. maximum number of display pixels at each duty ratio duty ratio maximum number of display pixel 80 dots or 8 segment lcd 10 digits 120 dots or 8 segment lcd 15 digits 160 dots or 8 segment lcd 20 digits 2 3 4 s e g m e n t o u t p u t e n a b l e b i t 0 0 : o u t p u t p o r t s p 3 0 p 3 5 1 : s e g m e n t o u t p u t s e g 1 8 s e g 2 3 s e g m e n t o u t p u t e n a b l e b i t 1 0 : o u t p u t p o r t s p 3 6 , p 3 7 1 : s e g m e n t o u t p u t s e g 2 4 , s e g 2 5 s e g m e n t o u t p u t e n a b l e b i t 2 0 : o u t p u t p o r t s p 0 0 p 0 5 1 : s e g m e n t o u t p u t s e g 2 6 s e g 3 1 s e g m e n t o u t p u t e n a b l e b i t 3 0 : o u t p u t p o r t s p 0 6 , p 0 7 1 : s e g m e n t o u t p u t s e g 3 2 , s e g 3 3 s e g m e n t o u t p u t e n a b l e b i t 4 0 : o u t p u t p o r t p 1 0 1 : s e g m e n t o u t p u t s e g 3 4 s e g m e n t o u t p u t e n a b l e b i t 5 0 : o u t p u t p o r t s p 1 1 p 1 5 1 : s e g m e n t o u t p u t s e g 3 5 s e g 3 9 n o t u s e d ( r e t u r n 0 w h e n r e a d ) ( d o n o t w r i t e 1 t o t h i s b i t ) s egment output ena bl e reg i ster (seg : address 0038 16 ) b 7 b 0 lcd mo d e reg i ster (lm : address 0039 16 ) d uty rat i o se l ect i on bi ts 0 0 : not used 0 1 : 2 duty (use com 0 , com 1 ) 1 0 : 3 duty (use com 0 com 2 ) 1 1 : 4 duty (use com 0 com 3 ) bias control bit 0 : 1/3 bias 1 : 1/2 bias lcd enable bit 0 : lcd off 1 : lcd on voltage multiplier control bit 0 : voltage multiplier disable 1 : voltage multiplier enable lcd circuit divider division ratio selection bits 0 0 : clock input 0 1 : 2 division of clock input 1 0 : 4 division of clock input 1 1 : 8 division of clock input lcdck count source selection bit (note) 0 : f(x cin )/32 1 : f(x in )/8192 (f(x cin )/8192 in low-speed mode) n o t e : l c d c k i s a c l o c k f o r a l c d t i m i n g c o n t r o l l e r . b 7 b 0
single-chip 8-bit cmos microcomputer mitsubishi microcomputers 3825 group 34 fig. 31 block diagram of lcd controller/driver d a t a b u s t i m i n g c o n t r o l l e r l c d d i v i d e r f ( x i n ) / 8 1 9 2 ( f ( x c i n ) / 8 1 9 2 i n l o w - s p e e d m o d e ) f ( x c i n ) / 3 2 c o m 0 c o m 1 c o m 2 c o m 3 v s s v l 1 v l 2 v l 3 s e g 3 s e g 2 s e g 1 s e g 0 a d d r e s s 0 0 4 0 1 6 a d d r e s s 0 0 4 1 1 6 1 0 l c d c k l c d c k c o u n t s o u r c e s e l e c t i o n b i t l c d c i r c u i t d i v i d e r d i v i s i o n r a t i o s e l e c t i o n b i t s b i a s c o n t r o l b i t l c d e n a b l e b i t d u t y r a t i o s e l e c t i o n b i t s 2 2 s e l e c t o rs e l e c t o rs e l e c t o r s e l e c t o r s e l e c t o r s e l e c t o r l c d d i s p l a y r a m a d d r e s s 0 0 5 3 1 6 p 1 4 / s e g 3 8 p 3 0 / s e g 1 8 p 1 5 / s e g 3 9 l e v e l s h i f t l e v e l s h i f t l e v e l s h i f t l e v e l s h i f t l e v e l s h i f t l e v e l s h i f t c o m m o n d r i v e r c o m m o n d r i v e r c o m m o n d r i v e r c o m m o n d r i v e r c 1 c 2 v o l t a g e m u l t i p l i e r c o n t r o l b i t l e v e l s h i f t l e v e l s h i f t l e v e l s h i f t l e v e l s h i f t s e g m e n t d r i v e r s e g m e n t d r i v e r s e g m e n t d r i v e r s e g m e n t d r i v e r s e g m e n t d r i v e r s e g m e n t d r i v e r b i a s c o n t r o l
single-chip 8-bit cmos microcomputer mitsubishi microcomputers 3825 group 35 voltage multiplier (3 times) the voltage multiplier performs threefold boosting. this circuit in- puts a reference voltage for boosting from lcd power input pin v l1 . (however, when using a 1/2 bias, connect v l1 and v l2 and apply voltage by external resistor division.) the voltage multiplier control bit (bit 4 of the lcd mode register) controls the voltage multiplier. when voltage is input to the v l1 pin during operating the voltage multiplier, voltage that is twice as large as v l1 occurs at the v l2 pin, and voltage that is three times as large as v l1 occurs at the v l3 pin. when using the voltage multiplier; after applying 1.3 v voltage 2.3 v to the v l1 pin, set the voltage multiplier control bit to 1 to select the voltage multiplier enable. when not using the voltage multiplier, apply proper voltage to the lcd power input pins (v l1 v l3 ). bias control and applied voltage to lcd power input pins to the lcd power input pins (v l1 v l3 ), apply the voltage shown in table 11 according to the bias value. select a bias value by the bias control bit (bit 2 of the lcd mode register). common pin and duty ratio control the common pins (com 0 com 3 ) to be used are determined by duty ratio. select duty ratio by the duty ratio selection bits (bits 0 and 1 of the lcd mode register). fig. 32 example of circuit at each bias table 11. bias control and applied voltage to v l1 ? l3 bias value 1/3 bias 1/2 bias voltage value v l3 =v lcd v l2 =2/3 v lcd v l1 =1/3 v lcd v l3 =v lcd v l2 =v l1 =1/2 v lcd note : v lcd is the maximum value of supplied voltage for the lcd panel. table 12. duty ratio control and common pins used duty ratio 2 3 4 common pins used notes 1: com 2 and com 3 are open. 2: com 3 is open. bit 1 0 1 1 bit 0 1 0 1 com 0 , com 1 (note 1) com 0 com 2 (note 2) com 0 com 3 duty ratio selection bits v l 3 v l 2 c 2 c 1 v l 1 1 / 3 b i a s w h e n u s i n g t h e v o l t a g e m u l t i p l i e r v l3 v l2 c 2 c 1 v l1 1 / 3 b i a s w h e n n o t u s i n g t h e v o l t a g e m u l t i p l i e r o p e n o p e n r 2 r 1 r 3 r 1 = r 2 = r 3 c ontrast contro l v l 3 v l 2 c 2 c 1 v l 1 1/2 bi as o p e n o p e n r 4 r 5 r 4= r 5 c o n t r a s t c o n t r o l
single-chip 8-bit cmos microcomputer mitsubishi microcomputers 3825 group 36 lcd display ram address 0040 16 to 0053 16 is the designated ram for the lcd dis- play. when 1 are written to these addresses, the corresponding segments of the lcd display panel are turned on. lcd drive timing the lcdck timing frequency (lcd drive timing) is generated in- ternally and the frame frequency can be determined with the fol- lowing equation; (frequency of count source for lcdck) (divider division ratio for lcd) f(lcdck)= f(lcdck) duty ratio frame frequency= fig. 33 lcd display ram map 0 0 4 0 1 6 0 0 4 1 1 6 0 0 4 2 1 6 0 0 4 3 1 6 0 0 4 4 1 6 0 0 4 5 1 6 0 0 4 6 1 6 0 0 4 7 1 6 0 0 4 8 1 6 0 0 4 9 1 6 0 0 4 a 1 6 0 0 4 b 1 6 0 0 4 c 1 6 0 0 4 d 1 6 0 0 4 e 1 6 0 0 4 f 1 6 0 0 5 0 1 6 0 0 5 1 1 6 0 0 5 2 1 6 0 0 5 3 1 6 b i t add ress s e g 1 s e g 3 s e g 5 s e g 7 s e g 9 s e g 1 1 s e g 1 3 s e g 1 5 s e g 1 7 s e g 1 9 s e g 2 1 s e g 2 3 s e g 2 5 s e g 2 7 s e g 2 9 s e g 3 1 s e g 3 3 s e g 3 5 s e g 3 7 s e g 3 9 76543210 c o m 3 com 0 c o m 2 com 1 c o m 0 c o m 3 c o m 2 c o m 1 s e g 0 s e g 2 s e g 4 s e g 6 s e g 8 s e g 1 0 s e g 1 2 s e g 1 4 s e g 1 6 s e g 1 8 s e g 2 0 s e g 2 2 s e g 2 4 s e g 2 6 s e g 2 8 s e g 3 0 s e g 3 2 s e g 3 4 s e g 3 6 s e g 3 8
single-chip 8-bit cmos microcomputer mitsubishi microcomputers 3825 group 37 fig. 34 lcd drive waveform (1/2 bias) internal logic lcdck timing 1 / 4 d u t y v o l t a g e l e v e l v l 3 v l 2 = v l 1 v s s v l 3 v s s c o m 0 c o m 1 c o m 2 c o m 3 seg 0 off on off on com 3 com 2 com 1 com 0 com 3 com 2 com 1 com 0 1 / 3 d u t y v l3 v l2 =v l1 v ss v l3 v ss o f f o n on o f f o noff 1 / 2 d u t y com 0 c o m 1 c o m 2 s e g 0 c o m 0 c o m 1 s e g 0 v l 3 v l 2 = v l 1 v s s v l 3 v s s o f f o n off on off o n off o n c o m 0 c o m 2 com 1 com 0 com 2 com 1 com 0 c o m 2 c o m 1 c o m 0 com 1 com 0 com 1 com 0 com 1 c o m 0
single-chip 8-bit cmos microcomputer mitsubishi microcomputers 3825 group 38 fig. 35 lcd drive waveform (1/3 bias) i n t e r n a l l o g i c l c d c k t i m i n g 1 / 4 d u t y v o l t a g e l e v e l v l 3 v s s c o m 0 c o m 1 c o m 2 c o m 3 s e g 0 off on off on com 3 c o m 2 com 1 c o m 0 com 3 com 2 c o m 1 c o m 0 1 / 3 d u t y off o n o no f f o no f f 1/2 duty com 0 com 1 c o m 2 seg 0 c o m 0 com 1 s e g 0 off o n o f f o n o f f o n o f f on v l3 v l2 v ss v l1 v l3 v l2 v ss v l1 v l 3 v ss v l3 v l2 v ss v l1 v l3 v ss c o m 0 c o m 2 com 1 c o m 0 c o m 2 com 1 c o m 0 c o m 2 com 1 com 0 com 1 c o m 0 com 1 com 0 com 1 com 0
single-chip 8-bit cmos microcomputer mitsubishi microcomputers 3825 group 39 clock output function input/output ports p4 0 and p4 1 can output clock. the input/output ports and clock output function are put under double function con- trolled by the clock output control register (address 002a 16 ). selection of input/output ports and clock output function bits 0 and 1 of the clock output control register can select between the input/output ports and the clock output function. when selecting the clock output function, clocks are output while the direction register of ports p4 0 and p4 1 are set to output. at the next cycle of rewriting the clock output control bit, p4 0 is switched between the port output and the clock output. in synchronization with the fall of the clock (resulting from dividing x in by 5) on rewriting the clock output control bit, p4 1 is switched between the port output and the clock output. fig. 37 clock output function block diagram fig. 36 structure of clock output control register selection of output clock frequency bit 2 (output clock frequency selection bit) of the clock output con- trol register selects an output clock frequency. when setting the output clock frequency selection bit to 0 , port p4 0 becomes the frequency of f(x in ) and port p4 1 becomes the frequency of f(x in )/5. at this time, the output pulse of port p4 0 depends on the x in input pulse, while the output pulse of port p4 1 has duty ratio of about 40%. when setting the output clock frequency selection bit to 1 , port p4 0 becomes the frequency of f(x in )/2 and port p4 1 becomes the frequency of f(x in )/10. at this time, the output pulses of both ports p4 0 and p4 1 have duty ratio of 50%. p 4 0 c l oc k output contro l bi t 0 : i/o port 1 : clock output p4 1 clock output control bit 0 : i/o port 1 : clock output output clock frequency selection bit 0 : p4 0 f(x in ), p4 1 f(x in )/5 1 : p4 0 f(x in )/2, p4 1 f(x in )/10 not used (return 0 when read) cl oc k output contro l reg i ster (tcon : address 002a 16 ) b 7 b 0 p 4 0 1 / 2 p 4 0 d i r e c t i o n r e g i s t e r p 4 0 c l o c k o u t p u t c o n t r o l b i t 0 1 p 4 0 port l atc h 0 1 o u t p u t c l o c k f r e q u e n c y s e l e c t i o n b i t x in p 4 1 1 / 2 p 4 1 d i r e c t i o n r e g i s t e r p 4 1 c l o c k o u t p u t c o n t r o l b i t 0 1 p 4 1 p o r t l a t c h 0 1 o utput c l oc k frequency selection bit 1 / 5
single-chip 8-bit cmos microcomputer mitsubishi microcomputers 3825 group 40 fig. 39 internal state of microcomputer immediately after re- set fig. 38 example of reset circuit reset circuit to reset the microcomputer, reset pin should be held at an l level for 2 s or more. then the reset pin is returned to an h level (the power source voltage should be between v cc (min.) and 5.5 v, and the quartz-crystal oscillator should be stable), reset is released. after the reset is completed, the program starts from the address contained in address fffd 16 (high-order byte) and ad- dress fffc 16 (low-order byte). make sure that the reset input voltage meets v il spec. when a power source voltage passes v cc (min.). p o w e r o n p o w e r s o u r c e v o l t a g e r e s e t i n p u t v o l t a g e power source voltage detection circuit v i l s p e c . 0 v 0 v v cc r e s e t v cc reset n ote: th e contents o f a ll ot h er reg i sters an d ram are un d e fi ne d a f ter reset, so they must be initialized by software. ? : undefined r e g i s t e r c o n t e n t s a d d r e s s 0000 16 0002 16 0003 16 0004 16 0005 16 0006 16 0008 16 0009 16 000 a 16 000 b 16 0 0 0 c 1 6 0 0 0 d 1 6 000 e 16 0 0 0 f 1 6 0010 16 0011 16 0016 16 0017 16 0019 16 001 a 16 001 b 16 0020 16 0021 16 0022 16 0023 16 0024 16 0025 16 0026 16 0027 16 0028 16 0029 16 002 a 16 0034 16 0038 16 0039 16 003 a 16 003 b 16 0 0 3 c 1 6 0 0 3 d 1 6 003 e 16 0 0 3 f 1 6 ( p s ) ( p c h ) ( p c l ) ( 1 0 ) ( 1 1 ) ( 1 2 ) ( 1 3 ) ( 1 4 ) ( 1 5 ) ( 1 6 ) ( 1 7 ) ( 1 8 ) ( 1 9 ) ( 2 0 ) ( 21 ) ( 22 ) ( 23 ) ( 24 ) ( 25 ) ( 2 6 ) ( 2 7 ) ( 2 8 ) ( 2 9 ) ( 3 0 ) ( 3 1 ) ( 3 2 ) ( 3 3 ) ( 3 4 ) ( 1 ) ( 2 ) ( 3 ) ( 4 ) ( 5 ) ( 6 ) ( 7 ) ( 8 ) ( 9 ) ( 3 5 ) ( 3 6 ) ( 3 7 ) ( 3 8 ) ( 3 9 ) ( 4 0 ) ( 4 1 ) ( 4 2 ) ( 4 3 ) timer y (low) port p5 direction register port p6 port p6 direction register pull register b timer y (high) serial i/o control register uart control register timer x (high) timer x (low) timer x mode register timer y mode register timer 123 mode register serial i/o status register port p7 port p7 direction register port p8 a-d control register segment output enable register lcd mode register pull register a interrupt edge selection register cpu mode register interrupt request register 1 interrupt request register 2 interrupt control register 1 interrupt control register 2 processor status register program counter port p5 port p4 direction register port p4 port p3 port p2 direction register port p2 port p1 output control register port p1 port p0 port p8 direction register timer 1 timer 2 timer 3 clock output control register 111000 0 0 100000 0 0 000010 0 0 1 0 0 1 00 0 0 ? 1 ? ? ?? ?? 0 0 1 6 0 0 1 6 0 0 1 6 0 0 1 6 00 16 00 16 00 16 0 0 1 6 f f 1 6 f f 1 6 f f 1 6 f f 1 6 f f 1 6 0 1 1 6 ff 16 0 0 1 6 00 16 0 0 1 6 0 0 1 6 00 16 0 0 1 6 00 16 00 16 0 0 1 6 0 0 1 6 0 0 1 6 0 0 1 6 0 0 1 6 0 0 1 6 0 0 1 6 0 0 1 6 0 0 1 6 0 0 1 6 0 0 1 6 00 16 0 0 1 6 0 1 1 6 0 0 1 6 c o n t e n t s o f a d d r e s s f f f d 1 6 c o n t e n t s o f a d d r e s s f f f c 1 6
single-chip 8-bit cmos microcomputer mitsubishi microcomputers 3825 group 41 fig. 40 reset sequence ad l fffc fffd a d h , ? ? ? ? x in : a b out 8000 clock cycles n o t e s 1 : x i n a n d a r e i n t h e r e l a t i o n s h i p : f ( x i n ) = 8 f ( ) 2 : a q u e s t i o n m a r k ( ? ) i n d i c a t e s a n u n d e f i n e d s t a t u s t h a t d e p e n d s o n t h e p r e v i o u s s t a t u s . r e s e t a d d r e s s f r o m v e c t o r t a b l e r e s e t i n t e r n a l r e s e t a d d r e s s d a t a s y n c
single-chip 8-bit cmos microcomputer mitsubishi microcomputers 3825 group 42 clock generating circuit the 3825 group has two built-in oscillation circuits. an oscillation circuit can be formed by connecting a resonator between x in and x out (x cin and x cout ). use the circuit constants in accordance with the resonator manufacturer's recommended values. no exter- nal resistor is needed between x in and x out since a feed-back resistor exists on-chip. however, an external feed-back resistor is needed between x cin and x cout . to supply a clock signal externally, input it to the x in pin and make the x out pin open. the sub-clock x cin -x cout oscillation circuit cannot directly input clocks that are externally generated. accord- ingly, be sure to cause an external resonator to oscillate. immediately after poweron, only the x in oscillation circuit starts oscillating, and x cin and x cout pins function as i/o ports. frequency control (1) middle-speed mode the internal clock is the frequency of x in divided by 8. after reset, this mode is selected. (2)high-speed mode the internal clock is half the frequency of x in . (3) low-speed mode the internal clock is half the frequency of x cin . a low-power consumption operation can be realized by stopping the main clock x in in this mode. to stop the main clock, set bit 5 of the cpu mode register to 1 . when the main clock x in is restarted, set enough time for oscil- lation to stabilize by programming. note: if you switch the mode between middle/high-speed and low- speed, stabilize both x in and x cin oscillations. the suffi- cient time is required for the sub-clock to stabilize, espe- cially immediately after power-on and at returning from stop mode. when switching the mode between middle/high- speed and low-speed, set the frequency in the condition that f(x in ) > 3 f(x cin ). fig. 41 ceramic resonator circuit fig. 42 external clock input circuit oscillation control (1) stop mode if the stp instruction is executed, the internal clock stops at an h level, and x in and x cin oscillators stop. timer 1 is set to ff 16 and timer 2 is set to 01 16 . either x in or x cin divided by 16 is input to timer 1 as count source, and the output of timer 1 is connected to timer 2. the bits of the timer 123 mode register except bit 4 are cleared to 0 . set the timer 1 and timer 2 interrupt enable bits to disabled ( 0 ) before executing the stp instruction. oscillator restarts at reset or when an external interrupt is re- ceived, but the internal clock is not supplied to the cpu until timer 2 underflows. this allows time for the clock circuit oscillation to stabilize. (2) wait mode if the wit instruction is executed, the internal clock stops at an h level. the states of x in and x cin are the same as the state be- fore the executing the wit instruction. the internal clock restarts at reset or when an interrupt is received. since the oscillator does not stop, normal operation can be started immediately after the clock is restarted. x c i n c i n c o u t c c i n c c o u t r f rd x c o u t x i n x o u t x i n x o u t external oscillation circuit o p e n v cc v s s c c i n c c o u t rf r d x c i n x c o u t
single-chip 8-bit cmos microcomputer mitsubishi microcomputers 3825 group 43 fig. 43 clock generating circuit block diagram w i t i n s t r u c t i o n stp i nstruct i on ti m i ng (internal clock) s r q stp i nstruct i on s r q m a i n c l o c k s t o p b i t s r q t i m e r 2 ti mer 1 1 / 2 1/4 x i n x o u t x cout x c i n i nterrupt reques t r eset p o r t x c s w i t c h b i t 1 0 t i m e r 1 c o u n t s o u r c e s e l e c t i o n b i t ti mer 2 count source selection bit l o w - s p e e d m o d e m i d d l e - / h i g h - s p e e d m o d e i n t e r n a l s y s t e m c l o c k s e l e c t i o n b i t ( n o t e ) middl e-spee d mo d e h i g h - s p e e d m o d e o r l o w - s p e e d m o d e n ote: wh en us i ng t h e l ow-spee d mo d e, set t h e port x c sw i tc h bi t to 1 . m a i n c l oc k di v i s i on rat i o se l ect i on bi t 1 0 1 0 1 0 i n t e r r u p t d i s a b l e f l a g i 1 / 2 1 0
single-chip 8-bit cmos microcomputer mitsubishi microcomputers 3825 group 44 fig. 44 state transitions of internal clock s w i tc h t h e mo d e b y t h e a ll ows s h own b etween t h e mo d e bl oc k s. (d o not sw i tc h b etween t h e mo d e di rect l y w i t h out an a ll ow. ) 2: the all modes can be switched to the stop mode or the wait mode and returned to the source mode when the stop mode or the wait mode is ended. 3: timer and lcd operate in the wait mode. 4: when the stop mode is ended, a delay of approximately 1 ms occurs automatically by timer 1 and timer 2 in middle-/high-speed m ode. 5: when the stop mode is ended, a delay of approximately 0.25 s occurs automatically by timer 1 and timer 2 in low-speed mode. 6: wait until oscillation stabilizes after oscillating the main clock x in before the switching from the low-speed mode to middle-/high- speed mode. 7: the example assumes that 8 mhz is being applied to the x in pin and 32 khz to the x cin pin. f indicates the internal clock. cm 4 : p ort x c sw i tc h bi t 0: i/o port 1: x cin , x cout cm 5 : main clock (x in x out ) stop bit 0: oscillating 1: stopped cm 6 : main clock division ratio selection bit 0: f(x in )/2 (high-speed mode) 1: f(x in )/8 (middle-speed mode) cm 7 : internal system clock selection bit 0: x in x out selected (middle-/high-speed mode) 1: x cin x cout selected (low-speed mode ) cpu mo d e reg i ster (cpum : address 003b 16 ) b 7 b 4 r e s e t c m 6 0 1 c m 4 0 1 c m 7 = 0 ( 8 m h z s e l e c t e d ) c m 6 = 1 ( m i d d l e - s p e e d ) c m 5 = 0 ( 8 m h z o s c i l l a t i n g ) c m 4 = 0 ( 3 2 k h z s t o p p e d ) m i d d l e - s p e e d m o d e ( f ( ) = 1 m h z ) c m 7 = 0 ( 8 m h z s e l e c t e d ) c m 6 = 1 ( m i d d l e - s p e e d ) c m 5 = 0 ( 8 m h z o s c i l l a t i n g ) c m 4 = 1 ( 3 2 k h z o s c i l l a t i n g ) middle-speed mode (f( ) = 1 mhz) cm 7 = 0 (8 mhz selected) cm 6 = 0 (high-speed) cm 5 = 0 (8 mhz oscillating) cm 4 = 0 (32 khz stopped) high-speed mode (f( ) = 4 mhz) cm 7 = 0 (8 mhz selected) cm 6 = 0 (high-speed) cm 5 = 0 (8 mhz oscillating) cm 4 = 1 (32 khz oscillating) h i g h - s p e e d m o d e ( f ( ) = 4 m h z ) cm 7 = 1 (32 khz selected) cm 6 = 1 (middle-speed) cm 5 = 0 (8 mhz oscillating) cm 4 = 1 (32 khz oscillating) low-speed mode (f( ) =16 khz) cm 7 = 1 (32 khz selected) cm 6 = 0 (high-speed) cm 5 = 0 (8 mhz oscillating) cm 4 = 1 (32 khz oscillating) low-speed mode (f( ) =16 khz) cm 7 = 1 (32 khz selected) cm 6 = 1 (middle-speed) cm 5 = 1 (8 mhz stopped) cm 4 = 1 (32 khz oscillating) l o w - s p e e d m o d e ( f ( ) = 1 6 k h z ) cm 7 = 1 (32 khz selected) cm 6 = 0 (high-speed) cm 5 = 1 (8 mhz stopped) cm 4 = 1 (32 khz oscillating) low-speed mode (f( ) =16 khz) cm 6 0 1 cm 6 0 1 cm 6 0 1 c m 4 0 1 c m 7 0 1 c m 7 0 1 c m 5 0 1 c m 5 0 1 c m 4 c m 6 0 1 0 1 c m 4 c m 6 0 1 1 0 c m 5 c m 6 0 1 0 1 c m 5 c m 6 0 1 1 0
single-chip 8-bit cmos microcomputer mitsubishi microcomputers 3825 group 45 notes on programming processor status register the contents of the processor status register (ps) after a reset are undefined, except for the interrupt disable flag (i) which is 1 . af- ter a reset, initialize flags which affect program execution. in particular, it is essential to initialize the index x mode (t) and the decimal mode (d) flags because of their effect on calculations. interrupt the contents of the interrupt request bits do not change immedi- ately after they have been written. after writing to an interrupt re- quest register, execute at least one instruction before performing a bbc or bbs instruction. decimal calculations to calculate in decimal notation, set the decimal mode flag (d) to 1 , then execute an adc or sbc instruction. only the adc and sbc instructions yield proper decimal results. after executing an adc or sbc instruction, execute at least one instruction before executing a sec, clc, or cld instruction. in decimal mode, the values of the negative (n), overflow (v), and zero (z) flags are invalid. timers if a value n (between 0 and 255) is written to a timer latch, the fre- quency division ratio is 1/(n + 1). multiplication and division instructions the index mode (t) and the decimal mode (d) flags do not affect the mul and div instruction. the execution of these instructions does not change the contents of the processor status register. ports the contents of the port direction registers cannot be read. the following cannot be used: the data transfer instruction (lda, etc.) the operation instruction when the index x mode flag (t) is 1 the addressing mode which uses the value of a direction regis- ter as an index the bit-test instruction (bbc or bbs, etc.) to a direction register the read-modify-write instruction (ror, clb, or seb, etc.) to a direction register use instructions such as ldm and sta, etc., to set the port direc- tion registers. serial i/o in clock synchronous serial i/o, if the receive side is using an ex- ternal clock and it is to output the s rdy signal, set the transmit en- able bit, the receive enable bit, and the s rdy output enable bit to 1 . serial i/o continues to output the final bit from the t x d pin after transmission is completed. a-d converter the comparator uses internal capacitors whose charge will be lost if the clock frequency is too low. make sure that f(x in ) is at least 500khz during an a-d conversion. do not execute the stp or wit instruction during an a-d conver- sion. instruction execution time the instruction execution time is obtained by multiplying the fre- quency of the internal clock by the number of cycles needed to execute an instruction. the number of cycles required to execute an instruction is shown in the list of machine instructions. the frequency of the internal clock is half of the x in frequency.
single-chip 8-bit cmos microcomputer mitsubishi microcomputers 3825 group 46 data required for mask orders the following are necessary when ordering a mask rom produc- tion: 1.mask rom order confirmation form ? 2.mark specification form ? 3.data to be written to rom, in eprom form (three identical cop- ies) or one floppy disk. ? for the mask rom confirmation and the mark specifications, re- fer to the ?itsubishi mcu technical information?homepage (http://www.infomicom.mesc.co.jp/indexe.htm). rom programming method the built-in prom of the blank one time prom version and built- in eprom version can be read or programmed with a general- purpose prom programmer using a special programming adapter. set the address of prom programmer in the user rom area. table 13. programming adapter the prom of the blank one time prom version is not tested or screened in the assembly process and following processes. to en- sure proper operation after programming, the procedure shown in figure 45 is recommended to verify programming. fig. 45 programming and testing of one time prom version package 100pfb-a 100p6q-a 100p6s-a 100d0 name of programming adapter pca4738h-100a pca4738g-100a pca4738f-100a pca4738l-100a programming with prom programmer screening (caution) (150 c for 40 hours) verification with prom programmer f u n c t i o n a l c h e c k i n t a r g e t d e v i c e t h e s c r e e n i n g t e m p e r a t u r e i s f a r h i g h e r t h a n t h e s t o r a g e t e m p e r a t u r e . n e v e r e x p o s e t o 1 5 0 c e x c e e d i n g 1 0 0 h o u r s . caution :
single-chip 8-bit cmos microcomputer mitsubishi microcomputers 3825 group 47 high-speed mode f(x in ) = 8 mhz middle-speed mode f(x in ) = 8 mhz low-speed mode power source voltage a-d conversion reference voltage analog power source voltage analog input voltage an 0 an 7 h input voltage p1 6 , p1 7 , p4 0 , p4 1 , p4 5 , p4 7 , p5 2 , p5 3 , p5 6 , p6 0 p6 7 , p7 0 p7 7 , p8 0 , p8 1 (cm 4 =0) h input voltage p2 0 p2 7 , p4 2 p4 4 , p4 6 , p5 0 , p5 1 , p5 4 , p5 5 , p5 7 h input voltage reset h input voltage x in l input voltage p1 6 , p1 7 , p4 0 , p4 1 , p4 5 , p4 7 , p5 2 , p5 3 , p5 6 , p6 0 p6 7 , p7 0 p7 7 , p8 0 , p8 1 (cm 4 =0) l input voltage p2 0 p2 7 , p4 2 p4 4 , p4 6 , p5 0 , p5 1 , p5 4 , p5 5 , p5 7 l input voltage reset l input voltage x in 5.5 5.5 5.5 v cc v cc v cc v cc v cc v cc 0.3v cc 0.2v cc 0.2v cc 0.2v cc v cc v ss v ref av ss v ia v ih v ih v ih v ih v il v il v il v il symbol parameter limits min. v v v v v v v v v v v v v unit 4.0 2.5 2.5 2.0 av ss 0.7v cc 0.8v cc 0.8v cc 0.8v cc 0 0 0 0 5.0 5.0 5.0 0 0 typ. max. power source voltage table 14. absolute maximum ratings (standard, one time prom version) 0.3 to 7.0 0.3 to v cc +0.3 0.3 to v cc +0.3 0.3 to v l2 v l1 to v l3 v l2 to 7.0 0.3 to 7.0 0.3 to v cc +0.3 0.3 to 7.0 0.3 to v cc 0.3 to v l3 0.3 to v cc +0.3 0.3 to 7.0 0.3 to v l3 0.3 to v cc +0.3 300 20 to 85 40 to 125 v v v v v v v v v v v v v v v mw c c power source voltage input voltage p1 6 , p1 7 , p2 0 p2 7 , p4 0 p4 7 , p5 0 p5 7 , p6 0 p6 7 , p8 0 , p8 1 input voltage p7 0 p7 7 input voltage v l1 input voltage v l2 input voltage v l3 input voltage c 1 , c 2 input voltage reset, x in output voltage c 1 , c 2 output voltage p0 0 p0 7 , p1 0 p1 5 , p3 0 p3 7 output voltage p1 6 , p1 7 , p2 0 p2 7 , p4 0 p4 7 , p5 0 p5 7 , p6 0 p6 7 , p7 1 p7 7 , p8 0 , p8 1 output voltage v l3 output voltage v l2 , seg 0 seg 17 output voltage x out power dissipation operating temperature storage temperature v cc v i v i v i v i v i v i v i v o v o v o v o v o v o pd topr tstg symbol parameter conditions ratings unit all voltages are based on v ss . output transistors are cut off. at output port at segment output t a = 25 c table 15. recommended operating conditions (standard, one time prom version) (v cc = 2.5 to 5.5 v, t a = 20 to 85 c, unless otherwise noted.) electrical characteristics (standard, one time prom version)
single-chip 8-bit cmos microcomputer mitsubishi microcomputers 3825 group 48 table 16. recommended operating conditions (standard, one time prom version) (v cc = 2.5 to 5.5 v, t a = 20 to 85 c, unless otherwise noted) 20 20 20 20 40 10 10 10 10 20 0.5 5.0 5.0 0.1 2.5 2.5 5.0 note 1: the total output current is the sum of all the currents flowing through all the applicable ports. the total average current is an aver- age value measured over 100 ms. the total peak current is the peak value of all the currents. 2: the peak output current is the peak current flowing in each port. 3: the average output current is an average value measured over 100 ms. 4: when the oscillation frequency has a duty cycle of 50%. 5: when using the microcomputer in low-speed mode, make sure that the sub-clock input oscillation frequency on condition that f(x cin ) < f(x in )/3. h total peak output current p0 0 p0 7 , p1 0 p1 7 , p2 0 p2 7 , p3 0 p3 7 (note 1) h total peak output current p4 0 p4 7 ,p5 0 p5 7 , p6 0 p6 7 , p7 1 p7 7 , p8 0 , p8 1 (note 1) l total peak output current p0 0 p0 7 , p1 0 p1 7 , p2 0 p2 7 , p3 0 p3 7 (note 1) l total peak output current p4 0 p4 7 ,p5 0 p5 7 , p6 0 p6 7 , p8 0 , p8 1 (note 1) l total peak output current p7 1 p7 7 (note 1) h total average output current p0 0 p0 7 ,p1 0 p1 7 , p2 0 p2 7 , p3 0 p3 7 (note 1) h total average output current p4 0 p4 7 , p5 0 p5 7 , p6 0 p6 7 , p7 1 p7 7 , p8 0 , p8 1 (note 1) l total average output current p0 0 p0 7 , p1 0 p1 7 , p2 0 p2 7 , p3 0 p3 7 (note 1) l total average output current p4 0 p4 7 , p5 0 p5 7 , p6 0 p6 7 , p8 0 , p8 1 (note 1) l total average output current p7 1 p7 7 (note 1) h peak output current p0 0 p0 7 , p1 0 p1 5 , p3 0 p3 7 (note 2) h peak output current p1 6 , p1 7 , p2 0 p2 7 , p4 0 p4 7 , p5 0 p5 7 , p6 0 p6 7 , p7 1 p7 7 , p8 0 , p8 1 (note 2) l peak output current p0 0 p0 7 , p1 0 p1 5 , p3 0 p3 7 (note 2) l peak output current p1 6 , p1 7 , p2 0 p2 7 , p4 0 p4 7 , p5 0 p5 7 , p6 0 p6 7 , p7 0 p7 7 , p8 0 , p8 1 (note 2) h average output current p0 0 p0 7 , p1 0 p1 5 , p3 0 p3 7 (note 3) h average output current p1 6 , p1 7 , p2 0 p2 7 , p4 0 p4 7 , p5 0 p5 7 , p6 0 p6 7 , p7 1 p7 7 , p8 0 , p8 1 (note 3) l average output current p0 0 p0 7 , p1 0 p1 5 , p3 0 p3 7 (note 3) l average output current p1 6 , p1 7 , p2 0 p2 7 , p4 0 p4 7 , p5 0 p5 7 , p6 0 p6 7 , p7 1 p7 7 , p8 0 , p8 1 (note 3) input frequency for timers x and y (duty cycle 50%) main clock input oscillation frequency (note 4) sub-clock input oscillation frequency (note 4, 5) i oh(peak) i oh(peak) i ol(peak) i ol(peak) i ol(peak) i oh(avg) i oh(avg) i ol(avg) i ol(avg) i ol(avg) i oh(peak) i oh(peak) i ol(peak) i ol(peak) i oh(avg) i oh(avg) i ol(avg) i ol(avg) f(cntr 0 ) f(cntr 1 ) f(x in ) f(x cin ) symbol parameter limits min. ma ma ma ma ma ma ma ma ma ma ma ma ma ma ma ma ma ma mhz mhz mhz mhz mhz khz unit typ. max. (4.0 v v cc 5.5 v) (v cc 4.0 v) high-speed mode (4.0 v v cc 5.5 v) high-speed mode (v cc 4.0 v) middle-speed mode 4.0 (2 ? v cc ) 4 8.0 (4 ? v cc ) 8 8.0 50 32.768 10
single-chip 8-bit cmos microcomputer mitsubishi microcomputers 3825 group 49 table 17. electrical characteristics (standard, one time prom version) (v cc =4.0 to 5.5 v, t a = 20 to 85 c, unless otherwise noted) v cc 2.0 v cc 1.0 v cc 2.0 v cc 0.5 v cc 1.0 30 6.0 30 6.0 v t+ v t v t+ v t v t+ v t i ih i ih i ih i il i il i il i il i load i leak note: when 1 is set to port x c switch bit (bit 4 of address 003b 16 ) of cpu mode register, the drive ability of port p8 0 is different from the value above mentioned. h output voltage p0 0 p0 7 , p1 0 p1 5 , p3 0 p3 7 h output voltage p1 6 , p1 7 , p2 0 p2 7 , p4 0 p4 7 , p5 0 p5 7 , p6 0 p6 7 , p7 1 p7 7 , p8 0 , p8 1 (note) l output voltage p0 0 p0 7 , p1 0 p1 5 , p3 0 p3 7 l output voltage p1 6 , p1 7 , p2 0 p2 7 ,p4 0 p4 7 , p5 0 p5 7 , p6 0 p6 7 , p7 1 p7 7 , p8 0 , p8 1 (note) hysteresis int 0 int 3 , adt, cntr 0, cntr 1, p2 0 p2 7 hysteresis s clk , r x d hysteresis reset h input current p1 6 , p1 7 , p2 0 p2 7 ,p4 0 p4 7 , p5 0 p5 7 , p6 0 p6 7 , p7 0 p7 7 , p8 0 , p8 1 h input current reset h input current x in l input current p1 6 , p1 7 , p2 0 p2 7 ,p4 0 p4 7 , p5 0 p5 7 , p6 0 p6 7 , p7 1 p7 7 , p8 0 , p8 1 l input current p7 0 l input current reset l input current x in output load current p0 0 p0 7 , p1 0 p1 5 , p3 0 p3 7 output leak current p0 0 p0 7 , p1 0 p1 5 , p3 0 p3 7 symbol parameter limits min. v unit 0.5 0.5 0.5 4.0 70 25 4.0 70 25 typ. max. i oh = 0.1 ma i oh = 25 a v cc = 2.5 v i oh = 5 ma i oh = 1.25 ma i oh = 1.25 ma v cc = 2.5 v i ol = 5 ma i ol = 1.25 ma i ol = 1.25 ma v cc = 2.5 v i ol = 10 ma i ol = 2.5 ma i ol = 2.5 ma v cc = 2.5 v reset: v cc =2.5 v to 5.5 v v i = v cc v i = v cc v i = v cc v i = v ss pull-ups off v cc = 5 v, v i = v ss pull-ups on v cc = 3 v, v i = v ss pull-ups on v i = v ss v i = v ss v cc = 5.0 v, v o = v cc , pull-downs on output transistors off v cc = 3.0 v, v o = v cc , pull-downs on output transistors off v o = v cc , pull-downs off output transistors off v o = v ss , pull-downs off output transistors off test conditions v oh v oh v ol v ol 2.0 0.5 1.0 2.0 0.5 1.0 5.0 5.0 5.0 140 45 5.0 5.0 140 45 5.0 5.0 v v v v v v v v v v v v v a a a a a a a a a a a a a
single-chip 8-bit cmos microcomputer mitsubishi microcomputers 3825 group 50 table 18. electrical characteristics (standard, one time prom version) (v cc =2.5 to 5.5 v, t a = 20 to 85 c, unless otherwise noted) ma ma a a a a a v a 13 3.2 36 14 22 9.0 1.0 10 2.3 6.0 50 high-speed mode, v cc = 5 v f(x in ) = 8 mhz f(x cin ) = 32.768 khz output transistors off a-d converter in operating high-speed mode, v cc = 5 v f(x in ) = 8 mhz (in wit state) f(x cin ) = 32.768 khz output transistors off a-d converter in operating low-speed mode, v cc = 5 v, t a 55 c f(x in ) = stopped f(x cin ) = 32.768 khz output transistors off low-speed mode, v cc = 5 v, t a = 25 c f(x in ) = stopped f(x cin ) = 32.768 khz (in wit state) output transistors off low-speed mode, v cc = 3 v, t a 55 c f(x in ) = stopped f(x cin ) = 32.768 khz output transistors off low-speed mode, v cc = 3 v, t a = 25 c f(x in ) = stopped f(x cin ) = 32.768 khz (in wit state) output transistors off all oscillation stopped (in stp state) output transistors off symbol parameter limits min. unit typ. max. t a = 25 c t a = 85 c test conditions i cc power source current 6.4 1.6 25 7.0 15 4.5 0.1 1.8 3.0 10 v ram ram retention voltage at clock stop mode 2.0 5.5 v when using voltage multiplier v l1 = 1.8 v v l1 < 1.3 v v l1 i l1 power source voltage power source current (v l1 ) (note) 1.3 note : when the voltage multiplier control bit of the lcd mode register (bit 4 at address 0039 16 ) is 1 .
single-chip 8-bit cmos microcomputer mitsubishi microcomputers 3825 group 51 table 19. a-d converter characteristics (standard, one time prom version) ( v cc = 4.0 to 5.5 v, v ss = 0 v, t a = 20 to 85 c, 4 mhz f(x in ) 8 mhz, in middle-/high-speed mode, unless otherwise noted.) symbol parameter limits min. unit typ. max. test conditions t conv r ladder i vref i ia resolution absolute accuracy (excluding quantization error) conversion time ladder resistor reference input current analog port input current v cc = v ref = 5 v 12 50 bits lsb s k ? a a f(x in ) = 8 mhz v ref = 5 v 12.5 (note) 35 150 8 2 100 200 5.0 note : when an internal trigger is used in middle-speed mode, it is 14 s.
single-chip 8-bit cmos microcomputer mitsubishi microcomputers 3825 group 52 2 125 45 40 250 105 105 80 80 800 370 370 220 100 note : when f(x in ) = 8 mhz and bit 6 of address 001a 16 is 1 (clock synchronous). divide this value by four when f(x in ) = 8 mhz and bit 6 of address 001a 16 is 0 (uart). reset input l pulse width main clock input cycle time (x in input) main clock input h pulse width main clock input l pulse width cntr 0 , cntr 1 input cycle time cntr 0 , cntr 1 input h pulse width cntr 0 , cntr 1 input l pulse width int 0 to int 3 input h pulse width int 0 to int 3 input l pulse width serial i/o clock input cycle time (note) serial i/o clock input h pulse width (note) serial i/o clock input l pulse width (note) serial i/o input set up time serial i/o input hold time t w(reset) t c(x in ) t wh(x in ) t wl(x in ) t c(cntr) t wh(cntr) t wl(cntr) t wh(int) t wl(int) t c(s clk ) t wh(s clk ) t wl(s clk ) t su(r x d s clk ) t h(s clk r x d) symbol parameter limits min. s ns ns ns ns ns ns ns ns ns ns ns ns ns unit typ. max. table 20. timing requirements 1 (standard, one time prom version) (v cc = 4.0 to 5.5 v, v ss = 0 v, t a = 20 to 85 c, unless otherwise noted.) 2 125 45 40 500/ (v cc 2) 250/ (v cc 2) 20 250/ (v cc 2) 20 230 230 2000 950 950 400 200 reset input l pulse width main clock input cycle time (x in input) main clock input h pulse width main clock input l pulse width cntr 0 , cntr 1 input cycle time cntr 0 , cntr 1 input h pulse width cntr 0 , cntr 1 input l pulse width int 0 to int 3 input h pulse width int 0 to int 3 input l pulse width serial i/o clock input cycle time (note) serial i/o clock input h pulse width (note) serial i/o clock input l pulse width (note) serial i/o input set up time serial i/o input hold time t w(reset) t c(x in ) t wh(x in ) t wl(x in ) t c(cntr) t wh(cntr) t wl(cntr) t wh(int) t wl(int) t c(s clk ) t wh(s clk ) t wl(s clk ) t su(r x d s clk ) t h(s clk r x d) symbol parameter limits min. s ns ns ns ns ns ns ns ns ns ns ns ns ns unit typ. max. note: when f(x in ) = 8 mhz and bit 6 of address 001a 16 is 1 (clock synchronous). divide this value by four when f(x in ) = 8 mhz and bit 6 of address 001a 16 is 0 (uart). table 21. timing requirements 2 (standard, one time prom version) (v cc = 2.5 to 4.0 v, v ss = 0 v, t a = 20 to 85 c, unless otherwise noted.)
single-chip 8-bit cmos microcomputer mitsubishi microcomputers 3825 group 53 notes 1 : when the p4 5 /t x d p-channel output disable bit of the uart control register (bit 4 of address 001b 16 ) is 0 . 2 : x out and x cout pins are excluded. serial i/o clock output h pulse width serial i/o clock output l pulse width serial i/o output delay time (note 1) serial i/o output valid time (note 1) serial i/o clock output rising time serial i/o clock output falling time cmos output rising time (note 2) cmos output falling time (note 2) 140 30 30 30 30 symbol parameter limits min. ns ns ns ns ns ns ns ns unit t c(s clk ) /2 30 t c(s clk ) /2 30 30 10 10 typ. max. t wh(s clk ) t wl(s clk ) t d(s clk t x d) t v(s clk t x d) t r(s clk ) t f(s clk ) t r(cmos) t f(cmos) table 22. switching characteristics 1 (standard, one time prom version) (v cc = 4.0 to 5.5 v, v ss = 0 v, t a = 20 to 85 c, unless otherwise noted.) ns ns ns ns ns ns ns ns unit notes 1 : when the p4 5 /t x d p-channel output disable bit of the uart control register (bit 4 of address 001b 16 ) is 0 . 2 : x out and x cout pins are excluded. serial i/o clock output h pulse width serial i/o clock output l pulse width serial i/o output delay time (note 1) serial i/o output valid time (note 1) serial i/o clock output rising time serial i/o clock output falling time cmos output rising time (note 2) cmos output falling time (note 2) 350 50 50 50 50 symbol parameter limits min. t c(s clk ) /2 50 t c(s clk ) /2 50 30 20 20 max. t wh(s clk ) t wl(s clk ) t d(s clk t x d) t v(s clk t x d) t r(s clk ) t f(s clk ) t r(cmos) t f(cmos) typ. table 23. switching characteristics 2 (standard, one time prom version) (v cc = 2.5 to 4.0 v, v ss = 0 v, t a = 20 to 85 c, unless otherwise noted.)
single-chip 8-bit cmos microcomputer mitsubishi microcomputers 3825 group 54 electrical characteristics (extended operating temperature version) power source voltage input voltage p1 6 , p1 7 , p2 0 p2 7 , p4 0 p4 7 , p5 0 p5 7 , p6 0 p6 7 , p8 0 , p8 1 input voltage p7 0 p7 7 input voltage v l1 input voltage v l2 input voltage v l3 input voltage c 1 , c 2 input voltage reset, x in output voltage c 1 , c 2 output voltage p0 0 p0 7 , p1 0 p1 5 , p3 0 p3 7 output voltage p1 6 , p1 7 , p2 0 p2 7 , p4 0 p4 7 , p5 0 p5 7 , p6 0 p6 7 , p7 1 p7 7 , p8 0 , p8 1 output voltage v l3 output voltage v l2 , seg 0 seg 17 output voltage x out power dissipation operating temperature storage temperature v cc v i v i v i v i v i v i v i v o v o v o v o v o v o pd topr tstg symbol parameter conditions ratings 0.3 to 7.0 0.3 to v cc +0.3 0.3 to v cc +0.3 0.3 to v l2 v l1 to v l3 v l2 to 7.0 0.3 to 7.0 0.3 to v cc +0.3 0.3 to 7.0 0.3 to v cc 0.3 to v l3 0.3 to v cc +0.3 0.3 to 7.0 0.3 to v l3 0.3 to v cc +0.3 300 40 to 85 65 to 150 unit all voltages are based on v ss . output transistors are cut off. at output port at segment output t a = 25 c v v v v v v v v v v v v v v v mw c c high-speed mode f(x in )=8 mhz middle-speed mode f(x in ) = 8 mhz low-speed mode power source voltage a-d conversion reference voltage analog power source voltage analog input voltage an 0 an 7 h input voltage p1 6 , p1 7 , p4 0 , p4 1 , p4 5 , p4 7 , p5 2 , p5 3 , p5 6 , p6 0 p6 7 , p7 0 p7 7 , p8 0 , p8 1 (cm 4 =0) h input voltage p2 0 p2 7 , p4 2 p4 4 , p4 6 , p5 0 , p5 1 , p5 4 , p5 5 , p5 7 h input voltage reset h input voltage x in l input voltage p1 6 , p1 7 , p4 0 , p4 1 , p4 5 , p4 7 , p5 2 , p5 3 , p5 6 , p6 0 p6 7 , p7 0 p7 7 , p8 0 , p8 1 (cm 4 =0) l input voltage p2 0 p2 7 , p4 2 p4 4 , p4 6 , p5 0 , p5 1 , p5 4 , p5 5 , p5 7 l input voltage reset l input voltage x in t a = 20 to 85 c t a = 40 to 20 c t a = 20 to 85 c t a = 40 to 20 c table 25. recommended operating conditions (extended operating temperature version) (v cc = 2.5 to 5.5 v, t a = 20 to 85 c, and v cc = 3.0 to 5.5 v, ta = 40 to 20 c, unless otherwise noted.) 5.5 5.5 5.5 5.5 5.5 v cc v cc v cc v cc v cc v cc 0.3v cc 0.2v cc 0.2v cc 0.2v cc v cc v ss v ref av ss v ia v ih v ih v ih v ih v il v il v il v il symbol parameter limits min. v v v v v v v v v unit 4.0 2.5 3.0 2.5 3.0 2.0 av ss 0.7v cc 0.8v cc 0.8v cc 0.8v cc 0 0 0 0 5.0 5.0 5.0 5.0 5.0 0 0 typ. max. power source voltage v v v v table 24. absolute maximum ratings (extended operating temperature version)
single-chip 8-bit cmos microcomputer mitsubishi microcomputers 3825 group 55 50 ma ma ma ma ma ma ma ma ma ma ma ma ma ma ma ma table 26. recommended operating conditions (extended operating temperature version) (v cc = 2.5 to 5.5 v, t a = 20 to 85 c, and v cc = 3.0 to 5.5 v, t a = 40 to 20 c, unless otherwise noted.) ma ma 20 20 20 20 40 10 10 10 10 20 0.5 5.0 5.0 10 0.1 2.5 2.5 5.0 4.0 h total peak output current p0 0 p0 7 , p1 0 p1 7 , p2 0 p2 7 , p3 0 p3 7 (note 1) h total peak output current p4 0 p4 7 ,p5 0 p5 7 , p6 0 p6 7 , p7 1 p7 7 , p8 0 , p8 1 (note 1) l total peak output current p0 0 p0 7 , p1 0 p1 7 , p2 0 p2 7 , p3 0 p3 7 (note 1) l total peak output current p4 0 p4 7 ,p5 0 p5 7 , p6 0 p6 7 , p8 0 , p8 1 (note 1) l total peak output current p7 1 p7 7 (note 1) h total average output current p0 0 p0 7 , p1 0 p1 7 , p2 0 p2 7 , p3 0 p3 7 (note 1) h total average output current p4 0 p4 7 , p5 0 p5 7 , p6 0 p6 7 , p7 0 p7 1 , p8 0 , p8 1 (note 1) l total average output current p0 0 p0 7 , p1 0 p1 7 , p2 0 p2 7 , p3 0 p3 7 (note 1) l total average output current p4 0 p4 7 , p5 0 p5 7 , p6 0 p6 7 , p8 0 , p8 1 (note 1) l total average output current p7 1 p7 7 (note 1) h peak output current p0 0 p0 7 , p1 0 p1 5 , p3 0 p3 7 (note 2) h peak output current p1 6 , p1 7 , p2 0 p2 7 , p4 0 p4 7 , p5 0 p5 7 , p6 0 p6 7 , p7 1 p7 7 , p8 0 , p8 1 (note 2) l peak output current p0 0 p0 7 , p1 0 p1 5 , p3 0 p3 7 (note 2) l peak output current p1 6 , p1 7 , p2 0 p2 7 , p4 0 p4 7 , p5 0 p5 7 , p6 0 p6 7 , p7 1 p7 7 , p8 0 , p8 1 (note 2) h average output current p0 0 p0 7 , p1 0 p1 5 , p3 0 p3 7 (note 3) h average output current p1 6 , p1 7 , p2 0 p2 7 , p4 0 p4 7 , p5 0 p5 7 , p6 0 p6 7 , p7 1 p7 7 , p8 0 , p8 1 (note 3) h average output current p0 0 p0 7 , p1 0 p1 5 , p3 0 p3 7 (note 3) h average output current p1 6 , p1 7 , p2 0 p2 7 , p4 0 p4 7 , p5 0 p5 7 , p6 0 p6 7 , p7 1 p7 7 , p8 0 , p8 1 (note 3) input frequency for timers x and y (duty cycle 50%) main clock input oscillation frequency (note 4) sub-clock input oscillation frequency (note 4, 5) notes 1 : the total output current is the sum of all the currents flowing through all the applicable ports. the total average current is an av- erage value measured over 100 ms. the total peak current is the peak value of all the currents. 2 : the peak output current is the peak current flowing in each port. 3 : the average output current is an average value measured over 100 ms. 4 : when the oscillation frequency has a duty cycle of 50%. 5 : when using the microcomputer in low-speed mode, make sure that the sub-clock input oscillation frequency on condition that f(x cin ) < f(x in )/3. i oh(peak) i oh(peak) i ol(peak) i ol(peak) i ol(peak) i oh(avg) i oh(avg) i ol(avg) i ol(avg) i ol(avg) i oh(peak) i oh(peak) i ol(peak) i ol(peak) i oh(avg) i oh(avg) i ol(avg) i ol(avg) f(cntr 0 ) f(cntr 1 ) f(x in ) f(x cin ) symbol parameter limits min. unit typ. max. (4.0 v v cc 5.5 v) (v cc 4.0 v) 32.768 high-speed mode (4.0 v v cc 5.5 v) high-speed mode (v cc 4.0 v) middle-speed mode (2 ? v cc ) 4 8.0 (4 ? v cc ) 8 8.0 mhz mhz mhz mhz mhz khz
single-chip 8-bit cmos microcomputer mitsubishi microcomputers 3825 group 56 table 27. electrical characteristics (extended operating temperature version) (v cc = 2.5 to 5.5 v, t a = 20 to 85 c, and v cc = 3.0 to 5.5v, t a = 40 to 20 c, unless otherwise noted) a a a a a v v v v v cc 2.0 v cc 0.9 v cc 2.0 v cc 0.5 v cc 0.9 v t+ v t v t+ v t v t+ v t i ih i ih i ih i il i il i il i il i load i leak note : when 1 is set to port x c switch bit (bit 4 of address 003b 16 ) of cpu mode register, the drive ability of port p8 0 is different from the value above mentioned. h output voltage p0 0 p0 7 , p1 0 p1 5 , p3 0 p3 7 h output voltage p1 6 , p1 7 , p2 0 p2 7 ,p4 0 p4 7 , p5 0 p5 7 , p6 0 p6 7 , p7 1 p7 7 , p8 0 , p8 1 (note) l output voltage p0 0 p0 7 , p1 0 p1 5 , p3 0 p3 7 l output voltage p1 6 , p1 7 , p2 0 p2 7 ,p4 0 p4 7 , p5 0 p5 7 , p6 0 p6 7 , p7 1 p7 7 , p8 0 , p8 1 (note) hysteresis int 0 int 3 , adt, cntr 0, cntr 1, p2 0 p2 7 hysteresis s clk , r x d hysteresis reset h input current p1 6 , p1 7 , p2 0 p2 7 ,p4 0 p4 7 , p5 0 p5 7 , p6 0 p6 7 , p7 0 p7 7 , p8 0 , p8 1 h input current reset h input current x in l input current p1 6 , p1 7 , p2 0 p2 7 ,p4 0 p4 7 , p5 0 p5 7 , p6 0 p6 7 , p7 1 p7 7 , p8 0 , p8 1 l input current p7 0 l input current reset l input current x in output load current p0 0 p0 7 , p1 0 p1 5 , p3 0 p3 7 output leak current p0 0 p0 7 , p1 0 p1 5 , p3 0 p3 7 symbol parameter limits min. v unit 0.5 0.5 0.5 4.0 70 25 4.0 70 25 typ. max. i oh = 2.5 ma i oh = 0.6 ma v cc = 3.0 v i oh = 5 ma i oh = 1.25 ma i oh = 1.25 ma v cc = 3.0 v i ol = 5 ma i ol = 1.25 ma i ol = 1.25 ma v cc = 3.0 v i ol = 10 ma i ol = 2.5 ma i ol = 2.5 ma v cc = 3.0 v reset: v cc =2.5 v to 5.5 v v i = v cc v i = v cc v i = v cc v i = v ss pull-ups off v cc = 5 v, v i = v ss pull-ups on v cc = 3 v, v i = v ss pull-ups on v i = v ss v i = v ss v cc = 5.0 v, v o = v cc , pull-downs on output transistors off v cc = 3.0 v, v o = v cc , pull-downs on output transistors off v o = v cc , pull-downs off output transistors off v o = v ss , pull-downs off output transistors off test conditions v oh v oh v ol v ol 2.0 0.5 1.1 2.0 0.5 1.1 5.0 5.0 5.0 140 45 5.0 5.0 170 55 5.0 5.0 v v v v v v v v v a a a a a a a a 30 6.0 30 6.0
single-chip 8-bit cmos microcomputer mitsubishi microcomputers 3825 group 57 ma ma a a a a a v a 13 3.2 36 14 22 9.0 1.0 10 2.3 6.0 50 high-speed mode, v cc = 5 v f(x in ) = 8 mhz f(x cin ) = 32.768 khz output transistors off a-d converter in operating high-speed mode, v cc = 5 v f(x in ) = 8 mhz (in wit state) f(x cin ) = 32.768 khz output transistors off a-d converter in operating low-speed mode, v cc = 5 v, t a 55 c f(x in ) = stopped f(x cin ) = 32.768 khz output transistors off low-speed mode, v cc = 5 v, t a = 25 c f(x in ) = stopped f(x cin ) = 32.768 khz (in wit state) output transistors off low-speed mode, v cc = 3 v, t a 55 c f(x in ) = stopped f(x cin ) = 32.768 khz output transistors off low-speed mode, v cc = 3 v, t a = 25 c f(x in ) = stopped f(x cin ) = 32.768 khz (in wit state) output transistors off all oscillation stopped (in stp state) output transistors off symbol parameter limits min. unit typ. max. t a = 25 c t a = 85 c test conditions i cc power source current 6.4 1.6 25 7.0 15 4.5 0.1 1.8 3.0 10 v ram ram retention voltage at clock stop mode 2.0 5.5 v when using voltage multiplier v l1 = 1.8 v v l1 < 1.3 v v l1 i l1 power source voltage power source current (v l1 ) (note) 1.3 note : when the voltage multiplier control bit of the lcd mode register (bit 4 at address 0039 16 ) is 1 . table 29. a-d converter characteristics (extended operating temperature version) (v cc = 4.0 to 5.5 v, v ss = 0 v, t a = 40 to 85 c, 4 mhz f(x in ) 8 mhz, in middle-/high-speed mode, unless otherwise noted.) table 28. electrical characteristics (extended operating temperature version) (v cc = 2.5 to 5.5 v, t a = 20 to 85 c, and v cc = 3.0 to 5.5 v, t a = 40 to 20 c, unless otherwise noted.) symbol parameter limits min. unit typ. max. test conditions t conv r ladder i vref i ia resolution absolute accuracy (excluding quantization error) conversion time ladder resistor reference input current analog iinput current v cc = v ref = 5 v 12 50 bits lsb s k ? a a f(x in ) = 8 mhz v ref = 5 v 12.5 (note) 35 150 8 2 100 200 5.0 note : when an internal trigger is used in middle-speed mode, it is 14 s.
single-chip 8-bit cmos microcomputer mitsubishi microcomputers 3825 group 58 table 30. timing reguirements 1 (extended operating temperature version) (v cc = 4.0 to 5.5 v, v ss = 0 v, t a = 40 to 85 c, unless otherwise noted.) 2 125 45 40 250 105 105 80 80 800 370 370 220 100 note : when f(x in ) = 8 mhz and bit 6 of address 001a 16 is 1 (clock synchronous). divide this value by four when f(x in ) = 8 mhz and bit 6 of address 001a 16 is 0 (uart). reset input l pulse width main clock input cycle time (x in input) main clock input h pulse width main clock input l pulse width cntr 0 , cntr 1 input cycle time cntr 0 , cntr 1 input h pulse width cntr 0 , cntr 1 input l pulse width int 0 to int 3 input h pulse width int 0 to int 3 input l pulse width serial i/o clock input cycle time (note) serial i/o clock input h pulse width (note) serial i/o clock input l pulse width (note) serial i/o input set up time serial i/o input hold time t w(reset) t c(x in ) t wh(x in ) t wl(x in ) t c(cntr) t wh(cntr) t wl(cntr) t wh(int) t wl(int) t c(s clk ) t wh(s clk ) t wl(s clk ) t su(r x d s clk ) t h(s clk r x d) symbol parameter limits min. s ns ns ns ns ns ns ns ns ns ns ns ns ns unit typ. max. table 31. timing reguirements 2 (extended operating temperature version) (v cc = 2.5 to 4.0 v, v ss = 0 v, t a = 20 to 85 c, and v cc = 3.0 to 4.0 v, v ss = 0 v, t a = 40 to 20 c, unless otherwise noted.) note: when f(x in ) = 8 mhz and bit 6 of address 001a 16 is 1 (clock synchronous). divide this value by four when f(x in ) = 8 mhz and bit 6 of address 001a 16 is 0 (uart). 2 125 45 40 500/ (v cc 2) 250/ (v cc 2) 20 250/ (v cc 2) 20 230 230 2000 950 950 400 200 reset input l pulse width main clock input cycle time (x in input) main clock input h pulse width main clock input l pulse width cntr 0 , cntr 1 input cycle time cntr 0 , cntr 1 input h pulse width cntr 0 , cntr 1 input l pulse width int 0 to int 3 input h pulse width int 0 to int 3 input l pulse width serial i/o clock input cycle time (note) serial i/o clock input h pulse width (note) serial i/o clock input l pulse width (note) serial i/o input set up time serial i/o input hold time t w(reset) t c(x in ) t wh(x in ) t wl(x in ) t c(cntr) t wh(cntr) t wl(cntr) t wh(int) t wl(int) t c(s clk ) t wh(s clk ) t wl(s clk ) t su(r x d s clk ) t h(s clk r x d) symbol parameter limits min. s ns ns ns ns ns ns ns ns ns ns ns ns ns unit typ. max.
single-chip 8-bit cmos microcomputer mitsubishi microcomputers 3825 group 59 table 32. switching characteristics 1 (extended operating temperature version) (v cc = 4.0 to 5.5 v, v ss = 0 v, t a = 40 to 85 c, unless otherwise noted.) notes 1 : when the p4 5 /t x d p-channel output disable bit of the uart control register (bit 4 of address 001b 16 ) is 0 . 2 : x out and x cout pins are excluded. serial i/o clock output h pulse width serial i/o clock output l pulse width serial i/o output delay time (note 1) serial i/o output valid time (note 1) serial i/o clock output rising time serial i/o clock output falling time cmos output rising time (note 2) cmos output falling time (note 2) 140 30 30 30 30 symbol parameter limits min. ns ns ns ns ns ns ns ns unit t c(s clk ) /2 30 t c(s clk ) /2 30 30 10 10 typ. max. t wh(s clk ) t wl(s clk ) t d(s clk t x d) t v(s clk t x d) t r(s clk ) t f(s clk ) t r(cmos) t f(cmos) table 33. switching characteristics 2 (extended operating temperature version) (v cc = 2.5 to 4.0 v, v ss = 0 v, t a = 20 to 85 c, and v cc = 3.0 to 4.0 v, v ss = 0 v, t a = 40 to 20 c, unless otherwise noted.) notes 1 : when the p4 5 /t x d p-channel output disable bit of the uart control register (bit 4 of address 001b 16 ) is 0 . 2 : x out and x cout pins are excluded. serial i/o clock output h pulse width serial i/o clock output l pulse width serial i/o output delay time (note 1) serial i/o output valid time (note 1) serial i/o clock output rising time serial i/o clock output falling time cmos output rising time (note 2) cmos output falling time (note 2) 350 50 50 50 50 symbol parameter limits min. ns ns ns ns ns ns ns ns unit t c(s clk ) /2 50 t c(s clk ) /2 50 30 20 20 max. t wh(s clk ) t wl(s clk ) t d(s clk t x d) t v(s clk t x d) t r(s clk ) t f(s clk ) t r(cmos) t f(cmos) typ.
single-chip 8-bit cmos microcomputer mitsubishi microcomputers 3825 group 60 (v cc = 2.2 to 5.5 v, t a = 20 to 85 c, unless otherwise noted.) table 34. absolute maximum ratings (m version) power source voltage input voltage p1 6 , p1 7 , p2 0 p2 7 , p4 0 p4 7 , p5 0 p5 7 , p6 0 p6 7 , p8 0 , p8 1 input voltage p7 0 p7 7 input voltage v l1 input voltage v l2 input voltage v l3 input voltage c 1 , c 2 input voltage reset, x in output voltage c 1 , c 2 output voltage p0 0 p0 7 , p1 0 p1 5 , p3 0 p3 7 output voltage p1 6 , p1 7 , p2 0 p2 7 , p4 0 p4 7 , p5 0 p5 7 , p6 0 p6 7 , p7 1 p7 7 p8 0 , p8 1 output voltage v l3 output voltage v l2 , seg 0 seg 17 output voltage x out power dissipation operating temperature storage temperature v cc v i v i v i v i v i v i v i v o v o v o v o v o v o pd topr tstg symbol parameter conditions ratings 0.3 to 7.0 0.3 to v cc +0.3 0.3 to v cc +0.3 0.3 to v l2 v l1 to v l3 v l2 to 7.0 0.3 to 7.0 0.3 to v cc +0.3 0.3 to 7.0 0.3 to v cc 0.3 to v l3 0.3 to v cc +0.3 0.3 to 7.0 0.3 to v l3 0.3 to v cc +0.3 300 20 to 85 40 to 125 unit all voltages are based on v ss . output transistors are cut off. at output port at segment output t a = 25 c v v v v v v v v v v v v v v v mw c c high-speed mode, f(x in )=8 mhz middle-speed mode, f(x in ) = 8 mhz low-speed mode table 35. recommended operating conditions (m version) 5.5 5.5 5.5 v cc v cc v cc v cc v cc v cc 0.3v cc 0.2v cc 0.2v cc 0.2v cc v cc symbol parameter limits min. v unit 4.0 2.2 2.2 2.0 av ss 0.7v cc 0.8v cc 0.8v cc 0.8v cc 0 0 0 0 5.0 5.0 5.0 0 0 typ. max. power source voltage power source voltage a-d conversion reference voltage analog power source voltage analog input voltage an 0 an 7 h input voltage p1 6 , p1 7 , p4 0 , p4 1 , p4 5 , p4 7 , p5 2 , p5 3 , p5 6 , p6 0 p6 7 , p7 0 p7 7 , p8 0 , p8 1 (cm 4 =0) h input voltage p2 0 p2 7 , p4 2 p4 4 , p4 6 , p5 0 , p5 1 , p5 4 , p5 5 , p5 7 h input voltage reset h input voltage x in l input voltage p1 6 , p1 7 , p4 0 , p4 1 , p4 5 , p4 7 , p5 2 , p5 3 , p5 6 , p6 0 p6 7 , p7 0 p7 7 , p8 0 , p8 1 (cm 4 =0) l input voltage p2 0 p2 7 , p4 2 p4 4 , p4 6 , p5 0 , p5 1 , p5 4 , p5 5 , p5 7 l input voltage reset l input voltage x in v ss v ref av ss v ia v ih v ih v ih v ih v il v il v il v il v v v v v v v v v v v v electrical characteristics (m version)
single-chip 8-bit cmos microcomputer mitsubishi microcomputers 3825 group 61 50 ma ma ma ma ma ma ma ma ma ma ma ma ma ma ma ma table 36. recommended operating conditions (m version) (v cc = 2.2 to 5.5 v, t a = 20 to 85 c, unless otherwise noted.) ma ma 20 20 20 20 40 10 10 10 10 20 0.5 5.0 5.0 10 0.1 2.5 2.5 5.0 4.0 h total peak output current p0 0 p0 7 , p1 0 p1 7 , p2 0 p2 7 , p3 0 p3 7 (note 1) h total peak output current p4 0 p4 7 ,p5 0 p5 7 , p6 0 p6 7 , p7 1 p7 7 , p8 0 , p8 1 (note 1) l total peak output current p0 0 p0 7 , p1 0 p1 7 , p2 0 p2 7 , p3 0 p3 7 (note 1) l total peak output current p4 0 p4 7 ,p5 0 p5 7 , p6 0 p6 7 , p8 0 , p8 1 (note 1) l total peak output current p7 1 p7 7 (note 1) h total average output current p0 0 p0 7 , p1 0 p1 7 , p2 0 p2 7 , p3 0 p3 7 (note 1) h total average output current p4 0 p4 7 , p5 0 p5 7 , p6 0 p6 7 , p7 1 p7 7 , p8 0 , p8 1 (note 1) l total average output current p0 0 p0 7 , p1 0 p1 7 , p2 0 p2 7 , p3 0 p3 7 (note 1) l total average output current p4 0 p4 7 , p5 0 p5 7 , p6 0 p6 7 , p8 0 , p8 1 (note 1) l total average output current p7 1 p7 7 (note 1) h peak output current p0 0 p0 7 , p1 0 p1 5 , p3 0 p3 7 (note 2) h peak output current p1 6 , p1 7 , p2 0 p2 7 , p4 0 p4 7 , p5 0 p5 7 , p6 0 p6 7 , p7 1 p7 7 , p8 0 , p8 1 (note 2) l peak output current p0 0 p0 7 , p1 0 p1 5 , p3 0 p3 7 (note 2) l peak output current p1 6 , p1 7 , p2 0 p2 7 , p4 0 p4 7 , p5 0 p5 7 , p6 0 p6 7 , p7 1 p7 7 , p8 0 , p8 1 (note 2) h average output current p0 0 p0 7 , p1 0 p1 5 , p3 0 p3 7 (note 3) h average output current p1 6 , p1 7 , p2 0 p2 7 , p4 0 p4 7 , p5 0 p5 7 , p6 0 p6 7 , p7 1 p7 7 , p8 0 , p8 1 (note 3) h average output current p0 0 p0 7 , p1 0 p1 5 , p3 0 p3 7 (note 3) h average output current p1 6 , p1 7 , p2 0 p2 7 , p4 0 p4 7 , p5 0 p5 7 , p6 0 p6 7 , p7 1 p7 7 , p8 0 , p8 1 (note 3) input frequency for timers x and y (duty cycle 50%) main clock input oscillation frequency (note 4) sub-clock input oscillation frequency (note 4, 5) notes 1 : the total output current is the sum of all the currents flowing through all the applicable ports. the total average current is an av- erage value measured over 100 ms. the total peak current is the peak value of all the currents. 2 : the peak output current is the peak current flowing in each port. 3 : the average output current is an average value measured over 100 ms. 4 : when the oscillation frequency has a duty cycle of 50%. 5 : when using the microcomputer in low-speed mode, make sure that the sub-clock input oscillation frequency on condition that f(x cin ) < f(x in )/3. i oh(peak) i oh(peak) i ol(peak) i ol(peak) i ol(peak) i oh(avg) i oh(avg) i ol(avg) i ol(avg) i ol(avg) i oh(peak) i oh(peak) i ol(peak) i ol(peak) i oh(avg) i oh(avg) i ol(avg) i ol(avg) f(cntr 0 ) f(cntr 1 ) f(x in ) f(x cin ) symbol parameter limits min. unit typ. max. (4.0 v v cc 5.5 v) (2.2 v v cc 4.0 v) 32.768 high-speed mode (4.0 v v cc 5.5 v) high-speed mode (2.2 v v cc 4.0 v) middle-speed mode (10 ? v cc 4) / 9 8.0 8.0 mhz mhz mhz mhz mhz khz (20 ? v cc 8) / 9
single-chip 8-bit cmos microcomputer mitsubishi microcomputers 3825 group 62 table 37. electrical characteristics (m version) (v cc = 2.2 to 5.5 v, t a = 20 to 85 c, unless otherwise noted) a a a a a v v v v v cc 2.0 v cc 0.8 v cc 2.0 v cc 0.5 v cc 0.8 v t+ v t v t+ v t v t+ v t i ih i ih i ih i il i il i il i il i load i leak note : when 1 is set to port x c switch bit (bit 4 of address 003b 16 ) of cpu mode register, the drive ability of port p8 0 is different from the value above mentioned. h output voltage p0 0 p0 7 , p1 0 p1 5 , p3 0 p3 7 h output voltage p1 6 , p1 7 , p2 0 p2 7 ,p4 0 p4 7 , p5 0 p5 7 , p6 0 p6 7 , p7 1 p7 7 , p8 0 , p8 1 (note) l output voltage p0 0 p0 7 , p1 0 p1 5 , p3 0 p3 7 l output voltage p1 6 , p1 7 , p2 0 p2 7 ,p4 0 p4 7 , p5 0 p5 7 , p6 0 p6 7 , p7 1 p7 7 , p8 0 , p8 1 (note) hysteresis int 0 int 3 , adt, cntr 0, cntr 1, p2 0 p2 7 hysteresis s clk , r x d hysteresis reset h input current p1 6 , p1 7 , p2 0 p2 7 ,p4 0 p4 7 , p5 0 p5 7 , p6 0 p6 7 , p7 0 p7 7 , p8 0 , p8 1 h input current reset h input current x in l input current p1 6 , p1 7 , p2 0 p2 7 ,p4 0 p4 7 , p5 0 p5 7 , p6 0 p6 7 , p7 0 p7 7 , p8 0 , p8 1 l input current p7 0 l input current reset l input current x in output load current p0 0 p0 7 , p1 0 p1 5 , p3 0 p3 7 output leak current p0 0 p0 7 , p1 0 p1 5 , p3 0 p3 7 symbol parameter limits min. v unit 0.5 0.5 0.5 4.0 70 25 4.0 70 25 typ. max. i oh = 2.5 ma i oh = 0.25 ma v cc = 2.2 v i oh = 5 ma i oh = 1.25 ma i oh = 1.25 ma v cc = 2.2 v i ol = 5 ma i ol = 1.25 ma i ol = 1.25 ma v cc = 2.2 v i ol = 10 ma i ol = 2.5 ma i ol = 2.5 ma v cc = 2.2 v reset: v cc =2.2 v to 5.5 v v i = v cc v i = v cc v i = v cc v i = v ss pull-ups off v cc = 5 v, v i = v ss pull-ups on v cc = 2.2 v, v i = v ss pull-ups on v i = v ss v i = v ss v cc = 5.0 v, v o = v cc , pull-downs on output transistors off v cc = 2.2 v, v o = v cc , pull-downs on output transistors off v o = v cc , pull-downs off output transistors off v o = v ss , pull-downs off output transistors off test conditions v oh v oh v ol v ol 2.0 0.5 0.8 2.0 0.5 0.8 5.0 5.0 5.0 140 45 5.0 5.0 140 45 5.0 5.0 v v v v v v v v v a a a a a a a a 30 6.0 30 6.0
single-chip 8-bit cmos microcomputer mitsubishi microcomputers 3825 group 63 ma ma a a a a a v a 13 3.2 36 14 22 9.0 1.0 10 2.3 6.0 50 high-speed mode, v cc = 5 v f(x in ) = 8 mhz f(x cin ) = 32.768 khz output transistors off a-d converter in operating high-speed mode, v cc = 5 v f(x in ) = 8 mhz (in wit state) f(x cin ) = 32.768 khz output transistors off a-d converter in operating low-speed mode, v cc = 5 v, t a 55 c f(x in ) = stopped f(x cin ) = 32.768 khz output transistors off low-speed mode, v cc = 5 v, t a = 25 c f(x in ) = stopped f(x cin ) = 32.768 khz (in wit state) output transistors off low-speed mode, v cc = 3 v, t a 55 c f(x in ) = stopped f(x cin ) = 32.768 khz output transistors off low-speed mode, v cc = 3 v, t a = 25 c f(x in ) = stopped f(x cin ) = 32.768 khz (in wit state) output transistors off all oscillation stopped (in stp state) output transistors off symbol parameter limits min. unit typ. max. t a = 25 c t a = 85 c test conditions i cc power source current 6.4 1.6 25 7.0 15 4.5 0.1 1.8 3.0 10 v ram ram retention voltage at clock stop mode 2.0 5.5 v when using voltage multiplier v l1 = 1.8 v v l1 < 1.3 v v l1 i l1 power source voltage power source current (v l1 ) (note) 1.3 note : when the voltage multiplier control bit of the lcd mode register (bit 4 at address 0039 16 ) is 1 . table 39. a-d converter characteristics (m version) (v cc = 4.0 to 5.5 v, v ss = 0 v, t a = 20 to 85 c, 4 mhz f(x in ) 8 mhz, in middle-/high-speed mode, unless otherwise noted.) table 38. electrical characteristics (m version) (v cc = 2.2 to 5.5 v, t a = 20 to 85 c, unless otherwise noted.) symbol parameter limits min. unit typ. max. test conditions t conv r ladder i vref i ia resolution absolute accuracy (excluding quantization error) conversion time ladder resistor reference input current analog iinput current v cc = v ref = 5 v 12 50 bits lsb s k ? a a f(x in ) = 8 mhz v ref = 5 v 12.5 (note) 35 150 8 2 100 200 5.0 note : when an internal trigger is used in middle-speed mode, it is 14 s.
single-chip 8-bit cmos microcomputer mitsubishi microcomputers 3825 group 64 table 40. timing reguirements 1 (m version) (v cc = 4.0 to 5.5 v, v ss = 0 v, t a = 20 to 85 c, unless otherwise noted.) 2 125 45 40 250 105 105 80 80 800 370 370 220 100 note : when f(x in ) = 8 mhz and bit 6 of address 001a 16 is 1 (clock synchronous). divide this value by four when f(x in ) = 8 mhz and bit 6 of address 001a 16 is 0 (uart). reset input l pulse width main clock input cycle time (x in input) main clock input h pulse width main clock input l pulse width cntr 0 , cntr 1 input cycle time cntr 0 , cntr 1 input h pulse width cntr 0 , cntr 1 input l pulse width int 0 to int 3 input h pulse width int 0 to int 3 input l pulse width serial i/o clock input cycle time (note) serial i/o clock input h pulse width (note) serial i/o clock input l pulse width (note) serial i/o input set up time serial i/o input hold time t w(reset) t c(x in ) t wh(x in ) t wl(x in ) t c(cntr) t wh(cntr) t wl(cntr) t wh(int) t wl(int) t c(s clk ) t wh(s clk ) t wl(s clk ) t su(r x d s clk ) t h(s clk r x d) symbol parameter limits min. s ns ns ns ns ns ns ns ns ns ns ns ns ns unit typ. max. table 41. timing reguirements 2 (m version) (v cc = 2.2 to 4.0 v, v ss = 0 v, t a = 20 to 85 c, unless otherwise noted.) note: when f(x in ) = 8 mhz and bit 6 of address 001a 16 is 1 (clock synchronous). divide this value by four when f(x in ) = 8 mhz and bit 6 of address 001a 16 is 0 (uart). 2 125 45 40 900 / (v cc 0.4) 450 / (v cc 0.4) 20 450 / (v cc 0.4) 20 230 230 2000 950 950 400 200 reset input l pulse width main clock input cycle time (x in input) main clock input h pulse width main clock input l pulse width cntr 0 , cntr 1 input cycle time cntr 0 , cntr 1 input h pulse width cntr 0 , cntr 1 input l pulse width int 0 to int 3 input h pulse width int 0 to int 3 input l pulse width serial i/o clock input cycle time (note) serial i/o clock input h pulse width (note) serial i/o clock input l pulse width (note) serial i/o input set up time serial i/o input hold time t w(reset) t c(x in ) t wh(x in ) t wl(x in ) t c(cntr) t wh(cntr) t wl(cntr) t wh(int) t wl(int) t c(s clk ) t wh(s clk ) t wl(s clk ) t su(r x d s clk ) t h(s clk r x d) symbol parameter limits min. s ns ns ns ns ns ns ns ns ns ns ns ns ns unit typ. max.
single-chip 8-bit cmos microcomputer mitsubishi microcomputers 3825 group 65 table 42. switching characteristics 1 (m version) (v cc = 4.0 to 5.5 v, v ss = 0 v, t a = 20 to 85 c, unless otherwise noted.) notes 1 : when the p4 5 /t x d p-channel output disable bit of the uart control register (bit 4 of address 001b 16 ) is 0 . 2 : x out and x cout pins are excluded. serial i/o clock output h pulse width serial i/o clock output l pulse width serial i/o output delay time (note 1) serial i/o output valid time (note 1) serial i/o clock output rising time serial i/o clock output falling time cmos output rising time (note 2) cmos output falling time (note 2) 140 30 30 30 30 symbol parameter limits min. ns ns ns ns ns ns ns ns unit t c(s clk ) /2 30 t c(s clk ) /2 30 30 10 10 typ. max. t wh(s clk ) t wl(s clk ) t d(s clk t x d) t v(s clk t x d) t r(s clk ) t f(s clk ) t r(cmos) t f(cmos) table 43. switching characteristics 2 (m version) (v cc = 2.2 to 4.0 v, v ss = 0 v, t a = 20 to 85 c, unless otherwise noted.) notes 1 : when the p4 5 /t x d p-channel output disable bit of the uart control register (bit 4 of address 001b 16 ) is 0 . 2 : x out and x cout pins are excluded. serial i/o clock output h pulse width serial i/o clock output l pulse width serial i/o output delay time (note 1) serial i/o output valid time (note 1) serial i/o clock output rising time serial i/o clock output falling time cmos output rising time (note 2) cmos output falling time (note 2) 350 50 50 50 50 symbol parameter limits min. ns ns ns ns ns ns ns ns unit t c(s clk ) /2 50 t c(s clk ) /2 50 30 20 20 max. t wh(s clk ) t wl(s clk ) t d(s clk t x d) t v(s clk t x d) t r(s clk ) t f(s clk ) t r(cmos) t f(cmos) typ. fig. 46 circuit for measuring output switching characteristics m e a s u r e m e n t o u t p u t p i n 1 0 0 p f c m o s o u t p u t n ote: wh en bi t 4 o f t h e uart contro l reg i ster ( a dd ress 001b 16 ) is 1 (n-channel open-drain output mode). n - c h a n n e l o p e n - d r a i n o u t p u t ( n o t e ) 1 k ? 1 0 0 p f m easurement output p i n
single-chip 8-bit cmos microcomputer mitsubishi microcomputers 3825 group 66 timing diagram fig. 47 timing diagram t w(reset) 0 . 8 v c c 0 . 2 v c c r e s e t t c(x in ) t c(cntr) t w h ( c n t r ) t w l ( c n t r ) 0 . 8 v c c 0.2 v c c c n t r 0 , c n t r 1 t wh(int) t w l ( i n t ) 0 . 8 v c c 0 . 2 v c c i n t 0 i n t 3 t wh(x in ) t w l ( x i n ) 0 . 8 v c c 0.2 v c c x i n t c(s clk ) t wl(s clk ) t wh(s clk ) 0 . 2 v c c 0.8 v c c s c l k t r t f t d ( s c l k - t x d ) t v ( s c l k - t x d ) t x d r x d 0 . 2 v c c 0 . 8 v c c t s u ( r x d - s c l k ) t h ( s c l k - r x d )
single-chip 8-bit cmos microcomputer mitsubishi microcomputers 3825 group 67 package outlines qfp100-p-1420-0.65 1.58 weight(g) jedec code eiaj package code lead material alloy 42 100p6s-a plastic 100pin 14 ? 20mm body qfp 0.1 0.2 symbol min nom max a a 2 b c d e h e l l 1 y b 2 dimension in millimeters h d a 1 0.35 i 2 1.3 m d 14.6 m e 20.6 10 0 0.1 1.4 0.8 0.6 0.4 23.1 22.8 22.5 17.1 16.8 16.5 0.65 20.2 20.0 19.8 14.2 14.0 13.8 0.2 0.15 0.13 0.4 0.3 0.25 2.8 0 3.05 e e e e c h e 1 30 31 81 50 80 51 h d d m d m e a f a 1 a 2 l 1 l y b 2 i 2 recommended mount pad detail f 100 x 0.13 b x m mmp lqfp100-p-1414-0.50 weight(g) 0.63 jedec code eiaj package code lead material cu alloy 100p6q-a plastic 100pin 14 ? 14mm body lqfp 0.1 0.2 symbol min nom max a a 2 b c d e h e l l 1 y b 2 dimension in millimeters h d a 1 0.225 i 2 0.9 m d 14.4 m e 14.4 10 0 0.1 1.0 0.7 0.5 0.3 16.2 16.0 15.8 16.2 16.0 15.8 0.5 14.1 14.0 13.9 14.1 14.0 13.9 0.175 0.125 0.105 0.28 0.18 0.13 1.4 0 1.7 e e e h e 1 76 75 51 50 26 25 h d d a f y 100 lp 0.45 0.6 0.25 0.75 0.08 x a3 b x m a 1 a 2 l 1 l detail f lp a3 c m d l 2 b 2 m e e recommended mount pad mmp
single-chip 8-bit cmos microcomputer mitsubishi microcomputers 3825 group 68 tqfp100-p-1212-0.40 weight(g) 0.37 jedec code eiaj package code lead material cu alloy 100pfb-a plastic 100pin 12 ? 12mm body tqfp symbol min nom max a a 2 b c d e h e l l 1 y b 2 dimension in millimeters h d a 1 0.15 0.1 0.225 i 2 1.0 m d 12.4 m e 12.4 10 0 0.08 0.07 1.0 0.6 0.5 0.4 14.2 14.0 13.8 14.2 14.0 13.8 0.4 12.1 12.0 11.9 12.1 12.0 11.9 0.175 0.125 0.105 0.23 0.18 0.13 1.0 0.05 1.2 e h e e d h d 1 25 75 76 100 26 50 51 f e a y l 1 a 1 a 2 l lp a3 detail f c lp 0.45 0.6 0.25 0.75 x a3 b x m m d e m e b 2 i 2 recommended mount pad mmp weight(g) jedec code eiaj package code 100d0 glass seal 100pin qfn 31 50 81 51 80 30 1 1.075typ 0.45typ 0.65typ index 3.5typ 5.0max 0.65typ 1.075typ 0.35typ 0.65typ 12.35 0.15 15.6 0.13 21.0 0.13 18.85 0.15 100
?2001 mitsubishi electric corp. specifications subject to change without notice. notes regarding these materials these materials are intended as a reference to assist our customers in the selection of the mitsubishi semiconductor product b est suited to the customer? application; they do not convey any license under any intellectual property rights, or any other rights, belonging to mitsubishi electric corporation or a third party. mitsubishi electric corporation assumes no responsibility for any damage, or infringement of any third-party? rights, origina ting in the use of any product data, diagrams, charts, programs, algorithms, or circuit application examples contained in these materials. all information contained in these materials, including product data, diagrams, charts, programs and algorithms represents inf ormation on products at the time of publication of these materials, and are subject to change by mitsubishi electric corporation without notice due to product improvements or other reasons. it is therefore recommended that c ustomers contact mitsubishi electric corporation or an authorized mitsubishi semiconductor product distributor for the latest product information before purchasing a product listed herein. the information described here may contain technical inaccuracies or typographical errors. mitsubishi electric corporation assu mes no responsibility for any damage, liability, or other loss rising from these inaccuracies or errors. please also pay attention to information published by mitsubishi electric corporation by various means, including the mitsubish i semiconductor home page (http://www.mitsubishichips.com). when using any or all of the information contained in these materials, including product data, diagrams, charts, programs, and algorithms, please be sure to evaluate all information as a total system before making a final decision on the applicability of the information and products. mitsubishi electric corporation assumes no responsibility for any damage, liability or other loss resulting from the information contained herein. mitsubishi electric corporation semiconductors are not designed or manufactured for use in a device or system that is used und er circumstances in which human life is potentially at stake. please contact mitsubishi electric corporation or an authorized mitsubishi semiconductor product distributor when considering the use of a product contained herei n for any specific purposes, such as apparatus or systems for transportation, vehicular, medical, aerospace, nuclear, or undersea repeater use. the prior written approval of mitsubishi electric corporation is necessary to reprint or reproduce in whole or in part these m aterials. if these products or technologies are subject to the japanese export control restrictions, they must be exported under a licen se from the japanese government and cannot be imported into a country other than the approved destination. any diversion or reexport contrary to the export control laws and regulations of japan and/or the country of destination is pro hibited. please contact mitsubishi electric corporation or an authorized mitsubishi semiconductor product distributor for further detai ls on these materials or the products contained therein. keep safety first in your circuit designs! mitsubishi electric corporation puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. trouble with semiconductors may lead to personal injury, fire or property damage. remember to give due consideration to safety when making your circuit designs, with a ppropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of non-flammable material or (iii) prevention against any malfunction or mishap. head office: 2-2-3, marunouchi, chiyoda-ku, tokyo 100-8310, japan
revision history 3825 group data sheet rev. date description page summary (1/1) 1.0 01/23/98 first edition 2.0 05/15/98 7 to 10 17 43 53 the followings are mainly revised: group expnasion (11) port p7 0 of port bock diagram name in table 11 the ??input current parameter of i il in tables 25 and 35 is not p7 0 ?7 7 but p7 1 p7 7 . low power source version is added. 2.1 07/13/99 3.0 12/11/00 1 1 4 6 7 8 9 10 10 11 to 13 20 24 34 40 40 42 43 45 46 46 48 50 57 60 to 65 60 61 63 ?2 clock generating circuits?of ?eatures?is partly eliminated. ?power source voltage?of ?eatures?is partly revised. ?unction?of ?cc, vss?into table 1 is partly revised. figure 4 is partly revised. clause name and explanations of ?roup expansion (standard, one time prom version, eprom version)?are partly revised. table 3 is partly eliminated. table 4 is partly eliminated. clause name and explanations of ?roup expansion (m version)?are partly revised. figure name of figure 7 is partly revised. explanations of ?entral processing unit (cpu)?are added. (12), (13), (14) into figure 15 is partly revised. figure 19 is partly revised. figure 31 is partly revised. explanations of ?eset circuit?are partly revised. figure 38 is partly revised. explanations of ?lock generating circuit?are partly eliminated. figure 43 is partly revised. explanations of ?ecimal calculations?of ?otes on programming?are partly eliminated. explanations of ?ata required for mask orders?are partly added. explanations of ?ata required for writing orders?in rev.2.1 are elimi- nated. note number of ? oh(avg) p0 0 ?0 7 , p1 0 ?1 5 , p3 0 ?3 7 ?into table 16 is revised. test conditions of icc into table 18 are partly revised. test conditions of icc into table 28 are partly revised. table names of tables 34 to 43 are partly revised. limits of avss into table 35 is partly revised. parameter of i oh(avg) into table 36 is partly revised. test conditions of icc into table 38 is partly revised. 3.1 02/06/01 22 24 30 46 explanations of notes on interrupts?are partly revised. figure 19 is partly revised. notes on serial i/o?is added. explanations of ?ata required for mask orders?are partly revised.

▲Up To Search▲

Price & Availability of M38259EFDFP

	To Download M38259EFDFP Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .